MT48LC8M16A2P-6A:G Micron Technology Inc, MT48LC8M16A2P-6A:G Datasheet - Page 41

• Manufacturer Part Number: MT48LC8M16A2P-6A:G
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2P-6A:G

• Density: 128 Mb
• Maximum Clock Rate: 167 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 165mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
CKE
H
H
L
L
n - 1
CKE
H
H
L
L
Truth Table 2 – CKE
Notes: 1–4
n
Notes:
Reading or writing
Current State
Clock suspend
Clock suspend
All banks idle
All banks idle
Power-down
Power-down
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
Self refresh
Self refresh
clock edge.
MAND
clock edge n + 1 (provided that
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the
period.
the next command at clock edge n + 1.
n
is the logic state of CKE at clock edge n; CKE
n
.
t
n
XSR period. A minimum of two NOP commands must be provided during
is the command registered at clock edge n, and ACTION
COMMAND INHIBIT or NOPX
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
See Table 9 on page 42
AUTO REFRESH
WRITE or NOP
41
Command
t
CKS is met).
X
X
X
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
n - 1
128Mb: x4, x8, x16 SDRAM
was the state of CKE at the previous
Maintain clock suspend
Maintain power-down
Maintain self refresh
Clock suspend entry
Power-down entry
Exit clock suspend
Exit power-down
Self refresh entry
Exit self refresh
Action
©1999 Micron Technology, Inc. All rights reserved.
n
n
is a result of COM-
Operations
t
Notes
XSR is
t
XSR
5
7
6