MT48LC8M16A2B4-75:G TR Micron Technology Inc, MT48LC8M16A2B4-75:G TR Datasheet - Page 33

• Manufacturer Part Number: MT48LC8M16A2B4-75:G TR
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2B4-75:G TR

• Density: 128 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 21:
Figure 22:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
WRITE-to-WRITE
Random WRITE Cycles
Notes:
a prefetch architecture. A WRITE command can be initiated on any clock cycle following
a previous WRITE command. Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 22 on page 33, or each subsequent
WRITE may be performed to a different bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 23 on page 34. Data n + 1 is either the
last of a burst of two or the last desired element of a longer burst.
COMMAND
1. DQM is LOW. Each WRITE command may be to any bank.
COMMAND
ADDRESS
ADDRESS
CLK
CLK
TRANSITIONING DATA
DQ
DQ
TRANSITIONING DATA
BANK,
WRITE
WRITE
COL n
BANK,
COL n
D
D
T0
T0
n
IN
n
IN
WRITE
BANK,
COL a
n + 1
NOP
T1
D
T1
D
a
IN
IN
33
DON’T CARE
BANK,
WRITE
WRITE
COL x
BANK,
COL b
D
T2
D
T2
x
b
IN
IN
DON’T CARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COL m
WRITE
BANK,
T3
D
m
IN
128Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
Operations