MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 58

DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray

MT48LC64M8A2TG-75 IT:C

Manufacturer Part Number
MT48LC64M8A2TG-75 IT:C
Description
DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC64M8A2TG-75 IT:C

Package
54TSOP-II
Density
512 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
512M (64M x 8)
Speed
133MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 42:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
COMMAND
A11, A12
BA0, BA1
A0–A9,
DQM/
CLK
A10
CKE
DQ
t CMS
t CKS
t AS
t AS
t AS
Alternating Bank Read Accesses
ACTIVE
BANK 0
T0
ROW
ROW
t CKH
t CMH
t AH
t AH
t AH
Notes:
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
t CK
T1
1. For this example, BL = 4, and CL = 2.
2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”
NOP
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK 0
T2
READ
t CMH
t CH
CAS Latency - BANK 0
T3
NOP
t LZ
t AC
58
BANK 3
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
m
t RCD - BANK 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
OUT
T5
NOP
m + 1
t OH
t AC
ENABLE AUTO PRECHARGE
COLUMN b 2
D
BANK 3
OUT
T6
512Mb: x4, x8, x16 SDRAM
READ
m + 2
t OH
t AC
CAS Latency - BANK 3
©2000 Micron Technology, Inc. All rights reserved.
t RP - BANK 0
D
OUT
T7
NOP
Timing Diagrams
m + 3
t OH
t AC
BANK 0
T8
ACTIVE
ROW
ROW
D
OUT
t RCD - BANK 0
Don’t Care
Undefined
t OH
t AC
b

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