MT48LC64M8A2TG-75 IT:C Micron Technology Inc, MT48LC64M8A2TG-75 IT:C Datasheet - Page 53

• Manufacturer Part Number: MT48LC64M8A2TG-75 IT:C
• Description: DRAM Chip SDRAM 512M-Bit 64Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC64M8A2TG-75 IT:C

• Package: 54TSOP-II
• Density: 512 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: -40 to 85 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 37:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
DQML, DQMU
Self Refresh Mode
COMMAND
BA0, BA1
A11,A12
A0–A9,
DQM/
Notes:
CKE
A10
CLK
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
ALL BANKS
PRECHARGE
BANK(S)
T0
1. No maximum time limit for self refresh;
2.
t CKH
t CMH
t
AH
t CK
t
XSR requires minimum of two clocks regardless of frequency or timing.
t RP
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
AUTO
T2
≥
CLK stable prior to exiting
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self refresh mode
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(Restart refresh time base)
t
RAS (MIN) applies to non-self refresh mode.
Tn + 1
Exit self refresh mode
NOP
t XSR
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or COMMAND
INHIBIT
To + 1
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
To + 2
REFRESH
AUTO
Timing Diagrams
Don’t Care