MT48LC2M32B2TG-7 IT:G TR Micron Technology Inc, MT48LC2M32B2TG-7 IT:G TR Datasheet - Page 58
![DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7 IT:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7 IT:G TR
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7 IT:G TR
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
86-TSOP
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1075-2
Figure 40:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
COMMAND
BA0, BA1
DQM 0-3
A0-A9
CKE
CLK
A10
DQ
t CKS
t CMS
t AS
t AS
t AS
READ – with Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 4 and CL = 2.
2. A8 and A9 = “Don’t Care.”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CMH
t CH
CAS Latency
T3
NOP
t LZ
t AC
58
T4
NOP
D
OUT
t OH
t AC
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
OUT
T5
NOP
m + 1
t OH
t AC
D
T6
OUT
NOP
m + 2
t OH
t AC
t RP
©2001 Micron Technology, Inc. All rights reserved.
D
T7
OUT
NOP
64Mb: x32 SDRAM
m + 3
t OH
Timing Diagrams
t HZ
T8
ROW
BANK
ACTIVE
ROW
DON’T CARE
UNDEFINED