MT48LC2M32B2TG-7 IT:G TR Micron Technology Inc, MT48LC2M32B2TG-7 IT:G TR Datasheet - Page 33
![DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7 IT:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7 IT:G TR
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7 IT:G TR
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
86-TSOP
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1075-2
Power-Down
Figure 22:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Terminating a WRITE Burst
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress (see Figure 24 on page 34). If power-down
occurs when all banks are idle, this mode is referred to as precharge power-down; if
power-down occurs when there is a row active in either bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and output buffers,
excluding CKE, for maximum power savings while in standby. The device may not
remain in the power-down state longer than the refresh period (
refresh operations are performed in this mode.
The power-down state is exited by registering an NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
ADDRESS
DQMs are LOW.
CLK
DQ
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
BURST
T1
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
T2
NEXT
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CKS).
©2001 Micron Technology, Inc. All rights reserved.
t
64Mb: x32 SDRAM
REF or
t
REF
Commands
AT
) since no