MT48LC2M32B2TG-7 IT:G Micron Technology Inc, MT48LC2M32B2TG-7 IT:G Datasheet - Page 23
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MT48LC2M32B2TG-7 IT:G
Manufacturer Part Number
MT48LC2M32B2TG-7 IT:G
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-7_ITG.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7 IT:G
Density
64 Mb
Maximum Clock Rate
143 MHz
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
Figure 10:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Consecutive READ Bursts
Note:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
T0
T0
T0
BANK,
COL n
BANK,
BANK,
READ
COL n
READ
COL n
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
CL = 3
23
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
T3
NOP
NOP
NOP
D
D
n + 2
D
n + 1
OUT
OUT
OUT
n
T4
T4
T4
BANK,
BANK,
BANK,
READ
COL b
READ
COL b
READ
COL b
X = 0 cycles
X = 1 cycle
D
n + 2
D
n + 1
D
n + 3
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
D
n + 2
D
n + 3
OUT
OUT
OUT
b
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
Commands
T7
NOP
D
OUT
b