MT48LC2M32B2TG-6:G Micron Technology Inc, MT48LC2M32B2TG-6:G Datasheet - Page 62
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MT48LC2M32B2TG-6:G
Manufacturer Part Number
MT48LC2M32B2TG-6:G
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2TG-6G.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-6:G
Density
64 Mb
Maximum Clock Rate
166 MHz
Package
86TSOP-II
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
0 to 70 °C
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/7.5/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC2M32B2TG-6:G
Manufacturer:
MT
Quantity:
20 000
Figure 44:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
DQML, DQMH
COMMAND
BA0, BA1
DQM /
A0-A9
CLK
CKE
A10
DQ
Single WRITE
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Notes:
T0
ROW
ROW
BANK
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 10ns is required between <D
3. A8 and A9 = “Don’t Care.”
t CK
to meet
T1
NOP
DISABLE AUTO PRECHARGE
t
WR.
t CMS
t CL
t DS
COLUMN m 3
WRITE
BANK
T2
D
IN
t CMH
t CH
t DH
m
t WR
62
IN
m> and the PRECHARGE command, regardless of frequency,
T3
NOP
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T4
T5
NOP
t RP
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Timing Diagrams
ACTIVE
ROW
T6
ROW
BANK
DON’T CARE