MT48LC16M16A2P-75 IT:D Micron Technology Inc, MT48LC16M16A2P-75 IT:D Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC16M16A2P-75 IT:D
Manufacturer Part Number
MT48LC16M16A2P-75 IT:D
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC16M16A2P-75_ITD.pdf
(87 pages)
Specifications of MT48LC16M16A2P-75 IT:D
Density
256 Mb
Maximum Clock Rate
133 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
6|5.4 ns
Operating Temperature
-40 to 85 °C
Organization
16Mx16
Address Bus
15b
Access Time (max)
6/5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Compliant
- Current page: 70 of 87
- Download datasheet (4Mb)
Figure 40: READ With Auto Precharge Interrupted by a WRITE
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Internal
States
Command
Note:
Address
Bank m
Bank n
DQM
CLK
DQ
1
1. DQM is HIGH at T2 to prevent D
active
Page
READ - AP
Bank n,
Bank n
T0
Col a
READ with burst of 4
Page active
NOP
CL = 3 (bank n)
T1
T2
NOP
70
T3
D
NOP
OUT
OUT
a + 1 from contending with D
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WRITE - AP
Bank m,
Col d
T4
Bank m
D
Interrupt burst, precharge
IN
WRITE with burst of 4
Transitioning data
T5
NOP
256Mb: x4, x8, x16 SDRAM
D
t
RP - bank n
IN
PRECHARGE Operation
T6
NOP
D
IN
© 1999 Micron Technology, Inc. All rights reserved.
IN
d at T4.
T7
NOP
D
t WR - bank m
Don’t Care
IN
Write-back
Idle
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