74HCT165D NXP Semiconductors, 74HCT165D Datasheet - Page 4

• Manufacturer Part Number: 74HCT165D
• Description: Shift Register Single 8-Bit Serial/Parallel to Serial 16-Pin SO Bulk
• Manufacturer: NXP Semiconductors

Specifications of 74HCT165D

• Package: 16SO
• Logic Function: Shift Register
• Logic Family: HCT
• Operation Mode: Serial/Parallel to Serial
• Direction Type: Uni-Directional
• Number Of Element Inputs: 9
• Number Of Elements Per Chip: 1
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 125 °C
• No. Of Elements: 1
• Ic Output Type: Standard
• Logic Case Style: SOIC
• No. Of Pins: 16
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +125°C
• Svhc: No
• Logic Type: Shift Register
• Shift Register Function: Parallel To Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 2.
7. Functional description
Table 3.
[1]
74HC_HCT165_3
Product data sheet
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
V
Operating modes
parallel load
serial shift
hold “do nothing”
CC
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Pin description
Function table
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
6.2 Pin description
Inputs
PL
L
L
H
H
H
H
H
H
[1]
CE
X
X
L
L
H
X
CP
X
X
L
L
X
H
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
Rev. 03 — 14 March 2008
DS
X
X
l
h
l
h
X
X
D0 to D7 Q0
L
H
X
X
X
X
X
X
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Qn registers
L
H
L
H
L
H
q0
q0
Q1 to Q6 Q7
L to L
H to H
q0 to q5
q0 to q5
q0 to q5
q0 to q5
q1 to q6
q1 to q6
Outputs
L
H
q6
q6
q6
q6
q7
q7
© NXP B.V. 2008. All rights reserved.
Q7
H
L
q6
q6
q6
q6
q7
q7
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