8523BGLF Integrated Device Technology (Idt), 8523BGLF Datasheet - Page 5

• Manufacturer Part Number: 8523BGLF
• Description: Clock Driver 2-IN HSTL 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8523BGLF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: CML|HCSL|HSTL|LVDS|LVPECL|SSTL
• Maximum Output Frequency: 650 MHz
• Operating Supply Voltage: 3.3 V

ICS8523 Data Sheet
Table 4D. LVPECL DC Characteristics, V
NOTE 1: Common mode input voltage is defined as V
Table 4E. HSTL DC Characteristics, V
NOTE 1: Outputs termination with 50Ω to ground.
AC Electrical Characteristics
Table 5. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross
points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS8523CG REVISION E JANUARY 24, 2011
Symbol
I
I
V
V
Symbol
V
V
V
V
Symbol
f
t
tjit
tsk(o)
tsk(pp)
t
odc
IH
IL
OUT
PD
R
OH
OL
OX
PP
CMR
SWING
/ t
F
Parameter
Output High Current;
NOTE 1
Output Low Current;
NOTE 1
Output
Crossover Voltage
Peak-to-Peak
Output Voltage Swing
Parameter
Input High Current
Input Low Current
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
DD
nPCLK
PCLK
nPCLK
PCLK
= 3.3V ± 5%, V
Test Conditions
DD
DD
= 3.3V ± 5%, V
Integration Range: 12kHz - 20MHz
Integration Range: 12kHz - 20MHz
= 3.3V ± 5%, V
IH
.
20% to 80% @ 50MHz
DDO
Test Conditions
f
f
OUT
OUT
= 1.8V ±0.2V, T
V
V
ƒ ≤ 650MHz
DD
DD
V
V
Test Conditions
DD
DD
= 100MHz,
= 120MHz,
DDO
= 3.465V, V
= 3.465V, V
40% x (V
= V
= V
DDO
= 1.8V ±0.2V, T
5
IN
IN
= 1.8V ±0.2V, T
= 3.465V
= 3.465V
Minimum
OH
0.75
IN
IN
0.9
A
0
– V
= 0V
= 0V
= 0°C to 70°C
OL
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
) + V
A
= 0°C to 70°C
OL
A
= 0°C to 70°C
Minimum
Minimum
Typical
-150
250
0.3
1.5
1.0
45
-5
60% x (V
©2011 Integrated Device Technology, Inc.
Typical
Typical
0.082
0.190
Maximum
OH
1.25
1.4
0.4
– V
Maximum
Maximum
OL
650
200
700
V
1.6
150
30
55
1.0
) + V
5
DD
OL
Units
Units
Units
MHz
ns
ps
ps
ps
ps
ps
µA
µA
µA
µA
%
V
V
V
V
V
V