8523BGLF Integrated Device Technology (Idt), 8523BGLF Datasheet
8523BGLF
Specifications of 8523BGLF
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8523BGLF Summary of contents
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Low Skew, 1-to-4, Differential-to-HSTL Fanout Buffer General Description The ICS8523 is a low skew, high performance 1-to-4 Differential-to-HSTL Fanout Buffer. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, ...
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ICS8523 Data Sheet Table 1. Pin Descriptions Number Name 1 GND Power 2 CLK_EN 3 CLK_SEL 4 CLK 5 nCLK 6 PCLK 7 nPCLK Unused 10 V Power DD 11, 12 nQ3, Q3 Output 13 ...
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ICS8523 Data Sheet Function Tables Table 3A. Control Input Function Table Inputs CLK_EN CLK_SEL After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure ...
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ICS8523 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...
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ICS8523 Data Sheet Table 4D. LVPECL DC Characteristics, V Symbol Parameter nPCLK I Input High Current IH PCLK nPCLK I Input Low Current IL PCLK V Peak-to-Peak Voltage PP V Common Mode Input Voltage; NOTE 1 CMR NOTE 1: Common ...
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ICS8523 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...
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ICS8523 Data Sheet Parameter Measurement Information 3.3V±5% 1.8V±0. DDO HSTL GND 0V 3.3V/1.8V Output Load AC Test Circuit nQx Qx nQy Qy tsk(o) Output Skew nCLK, nPCLK CLK, PCLK nQ[0:3] Q[0: Propagation Delay ICS8523CG REVISION ...
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ICS8523 Data Sheet Parameter Measurement Information, continued nQ[0:3] Q[0: PERIOD t PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input ...
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ICS8523 Data Sheet 3.3V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the V and V input requirements. Figures show interface CMR examples ...
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ICS8523 Data Sheet 3.3V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both signals must meet the V requirements. Figures show interface examples for the PCLK/ nPCLK input driven by ...
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ICS8523 Data Sheet Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ...
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ICS8523 Data Sheet Schematic Example Figure 5 shows a schematic example of the ICS8523. In this example, the input is driven by an IDT HSTL driver. The decoupling 3.3V R12 1K 1. Ohm Ohm ...
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ICS8523 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS8523. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8523 is the sum of the ...
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ICS8523 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the HSTL output pair. HSTL output driver circuit and termination are shown in Figure 6. V DDO Q1 Figure 6. HSTL ...
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ICS8523 Data Sheet Reliability Information Table 7. θ vs. Air Flow Table for a 20 Lead TSSOP JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ...
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... NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...
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ICS8523 Data Sheet Revision History Sheet Rev Table Page Description of Change T4D 5 HSTL table - added Characteristics table - t changed Max. from 2.0ns to 1.6ns Updated Figure 1, CLK_EN Timing ...
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ICS8523 Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...