83947AYI-147LF Integrated Device Technology (Idt), 83947AYI-147LF Datasheet
83947AYI-147LF
Specifications of 83947AYI-147LF
Related parts for 83947AYI-147LF
83947AYI-147LF Summary of contents
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... D CLK_EN CLK0 1 CLK1 CLK_SEL OE 83947AYI-147 LVCMOS/LVTTL F F EATURES • 9 LVCMOS/LVTTL outputs • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum output frequency: 250MHz • Output skew: 115ps (maximum) • Part-to-part skew: 500ps (maximum) • Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V • ...
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... ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS ABLE UTPUT NABLE AND LOCK 83947AYI-147 NABLE UNCTION ABLE www.idt.com 2 ICS83947I-147 KEW LVCMOS/LVTTL F ANOUT REV. A AUGUST 12, 2010 , UFFER KΩ Ω ...
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... 83947AYI-147 LVCMOS/LVTTL F 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the + 0 device. These ratings are stress specifications only. Functional + 0.5V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- 47.9°C/W (0 lfpm) istics is not implied ...
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... T 5A ABLE HARACTERISTICS Ø 5B ABLE HARACTERISTICS Ø 83947AYI-147 = V = 3.3V±0.3V -40°C 85° DDO ≤ > ≤ 2.5V ± 5 -40°C 85° DDO ≤ www.idt.com 4 ICS83947I-147 KEW LVCMOS/LVTTL F ANOUT REV. A AUGUST 12, 2010 , UFFER ...
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... As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 83947AYI-147 LVCMOS/LVTTL DDITIVE HASE ITTER the 1Hz band to the power in the fundamental ...
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... V DDO sk(pp ART TO ART KEW CLK0,CLK1 V DDO 2 Q0: ROPAGATION ELAY 2V 0.8V Clock t Outputs R 3. UTPUT ISE ALL IME 83947AYI-147 LVCMOS/LVTTL EASUREMENT NFORMATION 1.25V±5% SCOPE DDO Qx LVCMOS GND -1.25V±5% 2. UTPUT OAD V DDO UTPUT KEW V Q0:Q8 odc = UTPUT UTY 2V 20% 0.8V ...
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... VDD=3.3V VDDO=3.3V VDDO (U1-10) (U1-14) (U1-18 0.1u 0.1u 0.1u 83947AYI-147 LVCMOS/LVTTL F For the LVCMOS output drivers, only one termination example =3.3V. The is shown in this schematic. Additional termination approaches CC are shown in the LVCMOS Termination Application Note (refer to ICS website). VDDO Ohm 1 GND ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83947I-147 is: 1040 83947AYI-147 LVCMOS/LVTTL ELIABILITY NFORMATION 32 L LQFP ...
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... ACKAGE UTLINE UFFIX FOR ABLE ACKAGE θ θ θ θ θ Reference Document: JEDEC Publication 95, MS-026 83947AYI-147 LVCMOS/LVTTL F LQFP EAD D IMENSIONS ° www.idt.com 9 ICS83947I-147 KEW B ANOUT ° REV. A AUGUST 12, 2010 -9 TO UFFER ...
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... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 83947AYI-147 LVCMOS/LVTTL F ...
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... 83947AYI-147 www.idt.com 11 ICS83947I-147 KEW LVCMOS/LVTTL F ANOUT REV. A AUGUST 12, 2010 , UFFER ...
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... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 83947AYI-147 LVCMOS/LVTTL F Sales 800-345-7015 (inside USA) ...