83940DY-01LF Integrated Device Technology (Idt), 83940DY-01LF Datasheet

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83940DY-01LF

Manufacturer Part Number
83940DY-01LF
Description
Clock Driver 2-IN LVCMOS/LVTTL 32-Pin LQFP Tray
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 83940DY-01LF

Package
32LQFP
Configuration
1 x 2:1
Input Signal Type
CML/LVCMOS/LVPECL/LVTTL/SSTL
Maximum Output Frequency
250 MHz
Operating Supply Voltage
2.5|3.3 V
G
The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer. The ICS83940-01 has two
selectable clock inputs. The PCLK, nPCLK pair can accept
LVPECL, CML or SSTL input levels. The single ended clock
input accepts LVCMOS or LVTTL input levels. The low
impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased from 18 to 36 by
utilizing the ability of the outputs to drive two series
terminated lines.
The ICS83940-01 is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operating supply
modes. Guaranteed output and part-to-part skew
characteristics make the ICS83940-01 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
83940DY-01
B
LVCMOS_CLK
ENERAL
LOCK
CLK_SEL
nPCLK
PCLK
D
IAGRAM
D
ESCRIPTION
0
1
18
Q0:Q17
LVPECL-
www.idt.com
1
P
F
• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
• PCLK, nPCLK supports the following input types:
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
impedance
LVCMOS or LVTTL
LVPECL, CML, SSTL
packages
EATURES
IN
LVCMOS_CLK
TO
A
CLK_SEL
-LVCMOS / LVTTL F
SSIGNMENT
nPCLK
PCLK
GND
GND
V
V
DDO
DD
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940-01
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-01
OW
S
ANOUT
KEW
REV. A AUGUST 4, 2010
24
23
22
21
20
19
18
17
, 1-
B
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
TO
UFFER
DDO
-18

Related parts for 83940DY-01LF

83940DY-01LF Summary of contents

Page 1

... B D LOCK IAGRAM CLK_SEL PCLK 0 nPCLK LVCMOS_CLK 1 83940DY-01 LVPECL- -LVCMOS / LVTTL EATURES • Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance • Selectable LVCMOS_CLK or LVPECL clock inputs • LVCMOS_CLK supports the following input types: LVCMOS or LVTTL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • ...

Page 2

... ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS 3A ABLE LOCK ELECT UNCTION 3B ABLE LOCK NPUT UNCTION ABLE — 0 — 0 — 0 — 0 — — 83940DY-01 LVPECL- -LVCMOS / LVTTL ABLE — — — — " www.idt.com 2 ICS83940- KEW ANOUT REV. A AUGUST 4, 2010 - UFFER kΩ Ω " ...

Page 3

... LVPECL- -LVCMOS / LVTTL F TO 3.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the + 0.3V DD device. These ratings are stress specifications only. Functional + 0.3V operation of product at these conditions or any conditions be- DDO yond those listed in the DC Characteristics or AC Character- ± ...

Page 4

... T 4C ABLE HARACTERISTICS 5A ABLE HARACTERISTICS 83940DY-01 LVPECL- -LVCMOS / LVTTL 2.5V±5 0° 70° DDO 3.3V ± 5 0° 70° DDO ≤ ≤ > > ≤ ≤ > > ≤ ≤ < www.idt.com 4 ICS83940- KEW ANOUT ± REV. A AUGUST 4, 2010 - UFFER µ ...

Page 5

... T 5B 3.3V ± 5%, V ABLE HARACTERISTICS 83940DY-01 LVPECL- -LVCMOS / LVTTL 2.5V ± 5 0° A DDO ≤ ≤ > > ≤ ≤ > > < ≤ < www.idt.com 5 ICS83940- KEW B ANOUT 70° REV. A AUGUST 4, 2010 -18 TO UFFER ...

Page 6

... T 5C ABLE HARACTERISTICS 83940DY-01 LVPECL- -LVCMOS / LVTTL 2.5V±5 0° 70° DDO ≤ ≤ > > ≤ ≤ > > < ≤ f ≤ www.idt.com 6 ICS83940- KEW B ANOUT REV. A AUGUST 4, 2010 -18 TO UFFER ...

Page 7

... GND -1.25V±5% 2. UTPUT OAD EST IRCUIT PART 1 V DDO Qx 2 PART 2 V DDO sk(pp ART TO ART KEW 83940DY-01 LVPECL- -LVCMOS / LVTTL EASUREMENT NFORMATION 1.25V±5% 2.05V±5% SCOPE DDO Qx LVCMOS GND -1.25V±5% 3.3V/2.5V O UTPUT V DD SCOPE nPCLK PCLK GND ...

Page 8

... Clock t Outputs UTPUT ISE ALL IME V DDO 2 LVCMOS_CLK nPCLK PCLK V DDO 2 Q0:Q17 ROPAGATION ELAY 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO 80% Q0:Q17 20 UTPUT UTY YCLE www.idt.com 8 ICS83940- -18 OW KEW TO B ANOUT UFFER V DDO PERIOD 100% odc = t PERIOD / ULSE IDTH ERIOD REV. A AUGUST 4, 2010 ...

Page 9

... PCLK to ground. LVCMOS ONTROL INS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 83940DY-01 LVPECL- -LVCMOS / LVTTL PPLICATION NFORMATION A S ...

Page 10

... F 2E. PCLK/nPCLK I D IGURE NPUT RIVEN SSTL RIVER 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO suggested here are examples only. If the driver is from must meet the V another vendor, use their termination recommendation Please consult with the vendor of the driver component to confirm the driver termination requirements. ...

Page 11

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS83940-01 is: 819 83940DY-01 LVPECL- -LVCMOS / LVTTL ELIABILITY NFORMATION ...

Page 12

... ACKAGE UTLINE UFFIX FOR EAD ABLE ACKAGE θ θ θ θ θ Reference Document: JEDEC Publication 95, MS-026 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO LQFP D IMENSIONS ° www.idt.com 12 ICS83940- KEW TO B ANOUT UFFER ° REV. A AUGUST 4, 2010 -18 ...

Page 13

... Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 83940DY-01 LVPECL- ...

Page 14

... 83940DY-01 LVPECL- -LVCMOS / LVTTL www.idt.com 14 ICS83940- KEW ANOUT REV. A AUGUST 4, 2010 - UFFER ...

Page 15

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 83940DY-01 LVPECL- -LVCMOS / LVTTL F TO ...

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