49FCT805APYG Integrated Device Technology (Idt), 49FCT805APYG Datasheet - Page 6
49FCT805APYG
Manufacturer Part Number
49FCT805APYG
Description
Clock Buffer 10-OUT 20-Pin SSOP Tube
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.49FCT805APYG.pdf
(7 pages)
Specifications of 49FCT805APYG
Package
20SSOP
Number Of Outputs Per Chip
10
Maximum Input Frequency
80 MHz
Maximum Propagation Delay Time @ Maximum Cl
5.3@5V ns
Operating Supply Voltage
5 V
TEST CIRCUITS AND WAVEFORMS
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t
IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
OUTPUT
OUTPUT
INPUT
Generator
NORMALLY
NORMALLY
INPUT
Pulse
CONTROL
OUTPUT
OUTPUT
INPUT
HIGH
LOW
V
IN
CLO SED
SW ITCH
SW ITCH
Test Circuits for All Outputs
t
PLH
Enable and Disable Times
O PEN
t
ENABLE
P LH
R
Pulse Skew - t
t
t
T
PZL
P ZH
t
D.U.T.
t
SK
Package Delay
V
R
CC
(p) = t
1.5V
1.5V
3.5V
0V
V
PHL
OUT
t
-
PHZ
SK(P)
t
DISABLE
PLH
50pF
C
t
F
PHL
L
t
≤ 2.5ns; t
PLZ
t
PHL
500
500
0.3V
0.3V
t
F
R
≤ 2.5ns
1.5V
V
V
3V
0V
3.5V
0V
OL
OH
0.8V
2.0V
1.5V
V
V
1.5V
3V
0V
7V
OH
OL
1.5V
V
V
0V
1.5V
3V
OH
OL
6
SWITCH POSITION
DEFINITIONS:
C
R
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
L
T
PACKAGE 2
PACKAGE 1
= Load capacitance: includes jig and probe capacitance.
= Termination resistance: should be equal to Z
OUTPUT
OUTPUT 1
OUTPUT 2
OUTPUT
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
INPUT
INPUT
Disable HIGH
Enable HIGH
Disable LOW
Enable LOW
Test
t
SK
Part-to-Part Skew - t
t
t
(pp) = t
PLH1
SK
t
PLH 1
t
(o) = t
PLH 2
t
t
PLH2
SK (pp)
Output Skew
t
SK (o)
PLH2
PLH2
-
t
-
PLH1
t
PLH1
OUT
or
SK(PP)
or
of the Pulse Generator.
t
PH L2
t
PHL1
t
PHL2
t
t
PLH 1
PHL2
Switch
t
Closed
t
PHL2
SK(pp)
GND
-
t
-
PHL1
t
SK (o)
t
PHL1
V
V
V
V
3V
1.5V
1.5V
1.5V
0V
OH
O L
OH
O L
1.5V
V
1.5V
V
V
1.5V
V
3V
0V
OH
OH
OL
OL