49FCT805APYG Integrated Device Technology (Idt), 49FCT805APYG Datasheet - Page 5

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49FCT805APYG

Manufacturer Part Number
49FCT805APYG
Description
Clock Buffer 10-OUT 20-Pin SSOP Tube
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 49FCT805APYG

Package
20SSOP
Number Of Outputs Per Chip
10
Maximum Input Frequency
80 MHz
Maximum Propagation Delay Time @ Maximum Cl
5.3@5V ns
Operating Supply Voltage
5 V
NOTES:
1. Propagation delay range indicated by Min. and Max. limit is due to V
2. See test circuits and waveforms.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
Symbol
t
t
SK(PP)
t
SK(O)
SK(P)
t
t
t
t
t
t
PZH
PHZ
PLH
PHL
PZL
PLZ
t
t
R
F
Parameter
Propagation Delay
IN
Output Rise Time
Output Fall Time
Output skew: skew between outputs of all banks of
same package (inputs tied together)
Pulse skew: skew between opposite transitions
of same output (|t
Part-to-part skew: skew between outputs of different
packages at same power supply voltage,
temperature, package type and speed grade
Output Enable Time
OE
Output Disable Time
OE
A
A
A
to OAn, IN
to OAn, OE
to OAn, OE
B
PHL -–
to OBn
B
B
to OBn
to OBn
t
PLH
|)
CC
Conditions
, operating temperature and process parameters. These propagation delay limits do not imply skew.
R
C
L
L
= 500Ω
= 50pF
(2)
5
Min
1.5
1.5
1.5
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
.
FCT805
Max
5.6
1.5
1.5
0.7
1.5
1
8
7
.
(1)
Min
1.5
1.5
1.5
.
FCT805A
Max
5.3
1.5
1.5
0.7
1.5
1
8
7
.
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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