CA3127M Intersil, CA3127M Datasheet - Page 2

• Manufacturer Part Number: CA3127M
• Description: TRANSISTOR ARRAY NPN 16-SOIC
• Manufacturer: Intersil

Specifications of CA3127M

• Transistor Type: 5 NPN
• Voltage - Collector Emitter Breakdown (max): 15V
• Frequency - Transition: 1.15GHz
• Noise Figure (db Typ @ F): 3.5dB @ 100MHz
• Gain: 27dB ~ 30dB
• Power - Max: 85mW
• Dc Current Gain (hfe) (min) @ Ic, Vce: 35 @ 5mA, 6V
• Current - Collector (ic) (max): 20mA
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Absolute Maximum Ratings
The following ratings apply for each transistor in the device
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
Electrical Specifications
DC CHARACTERISTICS (For Each Transistor)
Collector-to-Base Breakdown Voltage
Collector-to-Emitter Breakdown Voltage
Collector-to-Substrate Breakdown-Voltage
Emitter-to-Base Breakdown Voltage (Note 3)
Collector-Cutoff-Current
Collector-Cutoff-Current
DC Forward-Current Transfer Ratio
Base-to-Emitter Voltage
Collector-to-Emitter Saturation Voltage
Magnitude of Difference in V
Magnitude of Difference in I
DYNAMIC CHARACTERISTICS
Noise Figure
Gain-Bandwidth Product
Collector-to-Base Capacitance
Collector-to-Substrate Capacitance
Emitter-to-Base Capacitance
Voltage Gain
Power Gain
Noise Figure
1. The collector of each transistor of the CA3127 is isolated from the substrate by an integral diode. The substrate (Terminal 5) must be connected to
2. θ
Collector-to-Emitter Voltage, V
Collector-to-Base Voltage, V
Collector-to-Substrate Voltage, V
Collector Current, I
the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
JA
is measured with the component mounted on an evaluation PC board in free air.
C
PARAMETER
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
B
BE
CBO
CEO
2
CIO
. . . . . . . . . . . . . . . . . . . . . . .20V
T A = 25°C
. . . . . . . . . . . . . . . . . . . . .15V
(Note 1) . . . . . . . . . . . . .20V
I
I
I
I
V
V
V
V
I
Q
V
f = 100kHz, R
V
V
V
V
V
Cascode Configuration
f = 100MHz, V+ = 12V, I
C
C
C1
E
C
CE
CB
CE
CE
CE
CE
CB
CI
BE
CE
1
= 10µA, I
= 1mA, I
= 10µA, I
= 10mA, I
and Q
= 10µA, I
= 6V, f = 1MHz
= 4V, f = 1MHz
= 10V I
= 10V, I
= 6V
= 6V
= 6V, I
= 6V, I
= 6V, f = 1MHz
= 6V, f = 10MHz, R
CA3127
CA3127
2
B
C
C
Matched
E
C
B
TEST CONDITIONS
E
B
B
= 0
= 1mA
= 5mA
= 0
= 0
= 0
S
= 0
= 1mA
= 0, I
= 500Ω, I
E
Thermal Information
Thermal Resistance (Typical, Note 2)
Maximum Power Dissipation, P
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Packages) . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
= 0
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(SOIC - Lead Tips Only)
L
C
C
I
I
I
I
I
I
= 1kΩ, I
C
C
C
C
C
C
= 1mA
= 1mA
= 5mA
= 1mA
= 0.1mA
= 5mA
= 1mA
= 0.1mA
C
= 1mA
0.71
0.66
0.60
MIN
20
15
20
35
40
35
27
4
-
-
-
-
-
-
-
-
-
-
-
-
D
(Any One Transistor). . . . . .85mW
See Fig.
TYP
0.81
0.76
0.70
0.26
1.15
5.7
0.5
0.2
2.2
3.5
32
24
60
88
90
85
28
30
5
-
-
MAX
0.91
0.86
0.80
0.50
0.5
40
5
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
θ
June 5, 2006
JA
UNITS
120
GHz
(°C/W)
mV
µA
µA
FN662.5
nA
dB
pF
pF
pF
dB
dB
dB
V
V
V
V
V
V
V
V