AD7722ASZ Analog Devices Inc, AD7722ASZ Datasheet - Page 17

• Manufacturer Part Number: AD7722ASZ
• Description: ADC Single Delta-Sigma 195KSPS 16-Bit Parallel/Serial 44-Pin MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD7722ASZ

• Package: 44MQFP
• Resolution: 16 Bit
• Sampling Rate: 195 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel|Serial (3-Wire)
• Input Type: Voltage
• Polarity Of Input Voltage: Unipolar|Bipolar
• Number Of Bits: 16
• Sampling Rate (per Second): 220k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 375mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Circuits
Figures 19 and 20 show two simple circuits for bipolar mode
operation. Both circuits accept a single-ended bipolar signal
source and create the necessary differential signals at the input
to the ADC.
The circuit in Figure 19 creates a 0 V to 2.5 V signal at the
V
1.25 V. For single-ended applications, best THD performance
is obtained with V
input to the AD7722 can also be driven differentially with a
complementary input, as shown in Figure 20.
In this case, the input common-mode voltage is set to 2.5 V.
The 2.5 V p-p full-scale differential input is obtained with a
1.25 V p-p signal at each input in antiphase. This configuration
minimizes the required output swing from the amplifier circuit
and is useful for single-supply applications.
REV. B
IN
0.625V
AIN =
1.25V
AIN =
(+) pin to form a differential signal around an initial bias of
Figure 19. Single-Ended Analog Input Circuit for
Bipolar Mode Operation
Figure 20. Single-Ended-to-Differential Analog
Input Circuit for Bipolar Mode Operation
1k
1k
1k
1k
R
R
OP275
12pF
OP275
IN
12pF
1/2
1/2
(–) set to 1.25 V rather than 2.5 V. The
1k
1k
1k
1k
OP275
1/2
12pF
374k
374k
OP275
OP07
12pF
1/2
1k
100nF
100nF
100nF
100nF
1nF
1nF
1nF
1nF
10nF
16
24
18
22
16
18
22
24
DIFFERENTIAL
INPUT = 2.5V p-p
V
VOLTAGE = 1.25V
V
REF2
V
REF1
DIFFERENTIAL
INPUT = 2.5V p-p
V
COMMON-MODE
VOLTAGE = 2.5V
IN
V
REF1
REF2
IN
IN
IN
IN
(–) BIAS
(–)
(+)
AD7722
(–)
AD7722
(+)
–17–
The 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously sampled. A resistor
in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Generation
The AD7722 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the ADC.
The connection diagram for use with the crystal is shown in
Figure 21. Consult the crystal manufacturer’s recommendation
for the load capacitors.
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the
sampling process. The connection diagram for an external clock
source (Figure 22) shows a series damping resistor connected
between the clock output and the clock input to the AD7722.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modulates
the input signal and raises the noise floor. The sampling clock
generator should be isolated from noisy digital circuits, grounded,
and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the analog
ground plane in a split-ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital ground
plane. If the clock signal is passed between its origin on a digital
ground plane to the AD7722 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. The jitter can cause degradation in the
signal-to-noise ratio and can also produce unwanted harmonics.
This can be remedied somewhat by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver, such as
the PECL. In either case, the original master system clock
should be generated from a low phase noise crystal oscillator.
Figure 22. External Clock Oscillator Connection
Figure 21. Crystal Oscillator Connection
CIRCUITRY
CLOCK
XTAL
AD7722
25 –150
1M
CLKIN
CLKIN
AD7722
AD7722