SCC2681AE1A44 NXP Semiconductors, SCC2681AE1A44 Datasheet - Page 16

• Manufacturer Part Number: SCC2681AE1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2681AE1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.5 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA

This field selects the baud rate clock for the Channel B receiver. The
Philips Semiconductors
CSRA[7:4] – Channel A Receiver Clock Select
This field selects the baud rate clock for the Channel A receiver as
follows (X1 rate at 3.6864 MHz):
(See also Table 5 for other rates to 115.2 kHz)
Rates will change in direct proportion to X1 at 3.6864 MHz.
The receiver clock is always a 16 clock except for CSRA[7] = 1111.
CSRA[3:0] – Channel A Transmitter Clock Select
This field selects the baud rate clock for the Channel A transmitter.
The field definition is as per CSR[7:4] except as follows:
The transmitter clock is always a 16 clock except for
CSR[3:0] = 1111.
CSRB – Channel B Clock Select Register
CSRB[7:4] – Channel B Receiver Clock Select
field definition is as per CSRA[7:4] except as follows:
The receiver clock is always a 16 clock except for CSRB[7:4] = 1111.
CSRB[3:0] – Channel B Transmitter Clock Select
This field selects the baud rate clock for the Channel B transmitter.
The field definition is as per CSRA[7:4] except as follows:
The transmitter clock is always a 16 clock except for
CSRB[3:0] = 1111.
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
CSRA[7:4]
CSRA[3:0]
CSRB[7:4]
CSRB[3:0]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
1110
1111
1110
1111
1110
1111
IP5–16
IP5–1
ACR[7] = 0
ACR[7] = 0
ACR[7] = 0
ACR[7] = 0
IP4–16
IP3–16
IP6–16
IP4–1
IP3–1
IP6–1
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
38.4k
110
200
300
600
50
IP5–16
IP5–1
Baud Rate
ACR[7] = 1
Baud Rate
ACR[7] = 1
Baud Rate
ACR[7] = 1
Baud Rate
ACR[7] = 1
IP4–16
IP3–16
IP6–16
IP4–1
IP3–1
IP6–1
134.5
1,200
2,000
2,400
4,800
1,800
9,600
19.2k
Timer
110
150
300
600
75
16
character being received will be lost. The command has no effect on
CRA – Channel A Command Register
CRA is a register used to supply commands to Channel A. Multiple
commands can be specified in a single write to CRA as long as the
commands are non-conflicting, e.g., the ‘enable transmitter’ and
‘reset transmitter’ commands cannot be specified in a single
command word.
CRA[7] – Not Used
Must be set to zero.
CRA[6:4] – Channel A Miscellaneous Command
The encoded value of this field may be used to specify a single
command as follows:
CRA[6:4] – COMMAND
000
001
010
011
100
101
110
111
CRA[3] – Disable Channel A Transmitter
This command terminates transmitter operation and reset the
TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state. A disable transmitter cannot be loaded.
CRA[2] – Enable Channel A Transmitter
Enables operation of the Channel A transmitter. The TxRDY status
bit will be asserted.
CRA[1] – Disable Channel A Receiver
This command terminates operation of the receiver immediately – a
the receiver status bits or any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is
disabled. See Operation section.
CRA[0] – Enable Channel A Receiver
Enables operation of the Channel A receiver. If not in the special
wake up mode, this also forces the receiver into the search for
start-bit state.
Note: Performing disable and enable at the same time results in
disable.
ware reset had been applied. The receiver is disabled and the
No command.
Reset MR pointer. Causes the Channel A MR pointer to point
to MR1.
Reset receiver. Resets the Channel A receiver as if a hard-
FIFO is flushed.
Reset transmitter. Resets the Channel A transmitter as if a
hardware reset had been applied.
Reset error status. Clears the Channel A Received Break,
Parity Error, and Overrun Error bits in the status register
(SRA[7:4]). Used in character mode to clear OE status (al-
though RB, PE and FE bits will also be cleared) and in block
mode to clear all error status after a block of data has been
received.
Reset Channel A break change interrupt. Causes the Chan-
nel A break detect change bit in the interrupt status register
(ISR[2]) to be cleared to zero.
Start break. Forces the TxDA output LOW (spacing). If the
transmitter is empty the start of the break condition will be
delayed up to two bit times. If the transmitter is active the
break begins when transmission of the character is com-
pleted. If a character is in the THR, the start of the break will
be delayed until that character, or any other loaded subse-
quently are transmitted. The transmitter must be enabled for
this command to be accepted.
Stop break. The TxDA line will go HIGH (marking) within two
bit times. TxDA will remain HIGH for one bit time before the
next character, if any, is transmitted.
SCC2681
Product data