SCC2681AC1N28 NXP Semiconductors, SCC2681AC1N28 Datasheet - Page 6

• Manufacturer Part Number: SCC2681AC1N28
• Description: UART 2-CH 5V 28-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2681AC1N28

• Package: 28PDIP
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.75 V
• Maximum Processing Temperature: 260 °C
• Maximum Supply Current: 10 mA

7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must
1. For operating at elevated temperatures, the device must be derated based on +150 C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a
4. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: C
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
Philips Semiconductors
AC CHARACTERISTICS
T
NOTES:
2004 Apr 06
amb
SYMBOL
SYMBOL
Dual asynchronous receiver/transmitter (DUART)
Reset Timing (Figure 3)
Bus Timing (Figure 4)
Port Timing (Figure 5)
Interrupt Timing (Figure 6)
Clock Timing (Figure 7)
Transmitter Timing (Figure 8)
Receiver Timing (Figure 10)
transition time of
0.8 V and 2.0 V as appropriate.
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
be negated for t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
t
f
t
f
t
t
t
t
RES
AS
AH
CS
CH
RW
DD
DF
DS
DH
RWD
PS
PH
PD
IR
CLK
CLK
CTC
CTC
RX
RX
TX
TX
TXD
TCS
RXS
RXH
= –40 C to +85 C
9
9
9
9
9
9
9
9
RWD
RESET pulse width
A0-A3 set-up time to RDN, WRN LOW
A0-A3 hold time from RDN, WRN LOW
CEN set-up time to RDN, WRN LOW
CEN hold time from RDN, WRN HIGH
WRN, RDN pulse width
Data valid after RDN LOW
Data bus floating after RDN HIGH
Data set-up time before WRN HIGH
Data hold time after WRN HIGH
HIGH time between READs and/or WRITE
Port input set-up time before RDN LOW
Port input hold time after RDN HIGH
Port output valid after WRN HIGH
INTRN (or OP3-OP7 when used as interrupts) negated from:
X1/CLK HIGH or LOW time
X1/CLK frequency
CTCLK (IP2) HIGH or LOW time
CTCLK (IP2) frequency
RxC HIGH or LOW time
RxC frequency (16 )
TxC HIGH or LOW time
TxC frequency (16 )
TxD output delay from TxC external clock input on IP pin
Output delay from TxC LOW at OP pin to TxD data output
RxD data setup time before RxC HIGH at external clock input on IP pin
RxD data hold time after RxC HIGH at external clock input on IP pin
20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (delta break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
1
to guarantee that any status register changes are valid.
; V
6
6
10
CC
L
= +5.0 V
= 150 pF, except interrupt outputs. Test condition for interrupt outputs: C
(1 )
(1 )
10%
2, 3, 4, 5
PARAMETER
PARAMETER
7, 8
6
Min
200
100
225
100
200
100
100
220
220
240
200
1.0
10
20
0
0
–
–
0
0
–
–
–
–
–
–
–
0
0
0
0
0
–
0
L
= 50 pF, R
LIMITS
3.6864
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
L
= 2.7 k to V
Max
SCC2681
175
100
400
300
300
300
300
300
300
350
150
4.0
4.0
2.0
1.0
2.0
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Product data
CC
.
UNIT
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns