SCC2681AC1A44 NXP Semiconductors, SCC2681AC1A44 Datasheet - Page 11

• Manufacturer Part Number: SCC2681AC1A44
• Description: UART 2-CH 5V 44-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of SCC2681AC1A44

• Package: 44PLCC
• Number Of Channels Per Chip: 2
• Maximum Data Rate: 0.1152 MBd
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage: 5 V
• Minimum Single Supply Voltage: 4.75 V
• Maximum Processing Temperature: 245 °C
• Maximum Supply Current: 10 mA
• No. Of Channels: 2
• Uart Features: Quadruple Buffered Receiver Data Register
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Data Rate: 115.2Kilobaud
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The operation of the DUART is programmed by writing control words
Philips Semiconductors
PROGRAMMING
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Table 1. SCC2681 Register Addressing
* See Table 5 for BRG Extended frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
2004 Apr 06
Dual asynchronous receiver/transmitter (DUART)
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
BRG Extend *
Rx Holding Register A (RHRA)
Input Port Change Register (IPCR)
Interrupt Status Register (ISR)
Counter/Timer Upper Value (CTU)
Counter/Timer Lower Value (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
1 /16 Test
Rx Holding Register B (RHRB)
Use for scratch pad
Input Ports IP0 to IP6
Start Counter Command
Stop Counter Command
READ (RDN = 0)
11
The pointer then remains at MR2x, so that subsequent accesses are
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1x, switches the pointer to MR2x.
always to MR2x unless the pointer is reset to MR1x as described
above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
Mode Register A (MR1A, MR2A)
Clock Select Register A (CSRA)
Command Register A (CRA)
Tx Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Register (IMR)
C/T Upper Preset Value (CRUR)
C/T Lower Preset Value (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Register B (CSRB)
Command Register B (CRB)
Tx Holding Register B (THRB)
Use for scratch pad
Output Port Conf. Register (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
WRITE (WRN = 0)
SCC2681
Product data