IRF9620SPBF Vishay, IRF9620SPBF Datasheet - Page 6

• Manufacturer Part Number: IRF9620SPBF
• Description: MOSFET P-CH 200V 3.5A D2PAK
• Manufacturer: Vishay

Specifications of IRF9620SPBF

• Transistor Polarity: P-Channel
• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 1.5 Ohm @ 1.5A, 10V
• Drain To Source Voltage (vdss): 200V
• Current - Continuous Drain (id) @ 25° C: 3.5A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 22nC @ 10V
• Input Capacitance (ciss) @ Vds: 350pF @ 25V
• Power - Max: 3W
• Mounting Type: Surface Mount
• Package / Case: D²Pak, TO-263 (2 leads + tab)
• Minimum Operating Temperature: - 55 C
• Configuration: Single
• Resistance Drain-source Rds (on): 1.5 Ohm @ 10 V
• Drain-source Breakdown Voltage: 200 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 3.5 A
• Power Dissipation: 3000 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Continuous Drain Current Id: -3.5A
• Drain Source Voltage Vds: -200V
• On Resistance Rds(on): 1.5ohm
• Rds(on) Test Voltage Vgs: -10V
• Threshold Voltage Vgs Typ: -4V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: *IRF9620SPBF

IRF9620S, SiHF9620S
Vishay Siliconix
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91083.
www.vishay.com
6
- 10 V
V
G
Fig. 18a - Basic Gate Charge Waveform
Q
GS
Charge
Q
Q
GD
G
Re-applied
voltage
Reverse
recovery
current
+
R
-
g
D.U.T.
• Compliment N-Channel of D.U.T. for driver
Note
a. V
Note
Driver gate drive
D.U.T. l
D.U.T. V
Inductor current
GS
= - 5 V for logic level and - 3 V drive devices
P.W.
SD
DS
waveform
waveform
Peak Diode Recovery dV/dt Test Circuit
Body diode forward drop
Ripple ≤ 5 %
Fig. 19 - For P-Channel
Period
Body diode forward
+
-
• dV/dt controlled by R
• I
• D.U.T. - device under test
current
SD
Diode recovery
controlled by duty factor “D”
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
dV/dt
current transformer
dI/dt
D =
-
g
Period
P.W.
+
12 V
Fig. 18b - Gate Charge Test Circuit
V
I
GS
V
V
SD
Same type as D.U.T.
GS
DD
Current regulator
= - 10 V
+
-
0.2 µF
V
DD
a
- 3 mA
Current sampling resistors
50 kΩ
0.3 µF
I
G
S10-1728-Rev. B, 02-Aug-10
Document Number: 91083
D.U.T.
I
D
+
-
V
DS