HEF4526BTD NXP Semiconductors, HEF4526BTD Datasheet - Page 2
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HEF4526BTD
Manufacturer Part Number
HEF4526BTD
Description
Counter ICs PROG 4B BCD DWN CNTR
Manufacturer
NXP Semiconductors
Datasheet
1.HEF4526BP652.pdf
(10 pages)
Specifications of HEF4526BTD
Counter Type
Binary Counters
Logic Family
HEF4526B
Number Of Bits
4
Counting Sequence
Down
Operating Supply Voltage
4.5 V to 15.5 V
Mounting Style
SMD/SMT
Package / Case
SOT-109
Other names
HEF4526BT,652
Philips Semiconductors
DESCRIPTION
The HEF4526B is a synchronous programmable 4-bit
binary down counter with an active HIGH and an active
LOW clock input (CP
load input (PL), four parallel inputs (P
feedback input (CF), four buffered parallel outputs (O
O
asynchronous master reset input (MR).
This device is a programmable, cascadable down counter
with a decoded TC output for divide-by-n applications. In
single stage applications the TC output is connected to PL.
CF allows cascade divide-by-n operation with no
additional gates required.
FAMILY DATA, I
See Family Specifications
January 1995
3
Programmable 4-bit binary down counter
), a terminal count output (TC) and an overriding
DD
LIMITS category MSI
0
, CP
1
), an asynchronous parallel
0
to P
3
), a cascade
Fig.1 Functional diagram.
0
to
2
Information on P
is HIGH, independent of all other input conditions except
MR, which must be LOW. When PL and CP
counter advances on a LOW to HIGH transition of CP
When PL is LOW and CP
on a HIGH to LOW transition of CP
counter is in the zero state (O
and CF is HIGH and PL is LOW. A HIGH on MR resets the
counter (O
conditions.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
0
to O
0
3
to P
= LOW) independent of other input
3
is loaded into the counter while PL
0
is HIGH, the counter advances
0
= O
1
Product specification
1
. TC is HIGH when the
= O
HEF4526B
2
= O
1
are LOW, the
3
= LOW)
MSI
0
.