LAN91C100FDTQFP SMSC, LAN91C100FDTQFP Datasheet - Page 36

• Manufacturer Part Number: LAN91C100FDTQFP
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FDTQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.0 (09-22-08)
3.
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2)
the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due to the
RCV DISCRD bit in the RCV register set. The RX_OVRN INT bit latches the condition for the purpose of
being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with
the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX RAM page is successful. This bit is the complement of the
FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the
next allocation request is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the end of a
sequence of packets enqueued for transmission. This bit latches the empty condition, and the bit will stay
set until it is specifically cleared by writing the acknowledge register with the TX EMPTY INT bit set. If a
real time reading of the FIFO empty is desired, the bit should be first cleared and then read.
The TX EMPTY Mask bit should only be set after the following steps:
a.
b.
TX INT - Set when at least one packet transmission was completed or any of the below transmit fatal
errors occurs:
1.
2.
3.
4.
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is
always the logic complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet
number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with the TX INT bit
set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read
from the FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the
FIFO PORTS register. The Receive Interrupt is cleared when RX FIFO is empty.
Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above (3.1
to 3.5).
a packet is enqueued for transmission
the previous empty condition is cleared (acknowledged)
SQET - SQE Error
LOST CARR - Lost Carrier
LATCOL - Late Collision
16COL - 16 collisions
DATASHEET
Page 36
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC LAN91C100FD Rev. D