LAN91C100FDTQFP SMSC, LAN91C100FDTQFP Datasheet
LAN91C100FDTQFP
Specifications of LAN91C100FDTQFP
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LAN91C100FDTQFP Summary of contents
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... Kbyte External Memory LAN91C100-FD for 208-pin QFP package LAN91C100-FD-SS for 208-pin QFP lead-free RoHS compliant package LAN91C100-FD for 208-pin TQFP package LAN91C100-FD-ST for 208-pin TQFP lead-free RoHS compliant package SMSC LAN91C100FD Rev. D LAN91C100FD REV. D FEAST Fast Ethernet Controller with Full Duplex Capability ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...
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... Figure 5.3 - Interrupt Service Routine ..........................................................................................................................44 Figure 5 INTR ...................................................................................................................................................45 Figure 5 INTR....................................................................................................................................................46 Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................47 Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................48 Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................51 Figure 6 Serial EEPROM Map...................................................................................................................54 SMSC LAN91C100FD Rev. D Page 3 DATASHEET Revision 1.0 (09-22-08) ...
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... Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors Table 7.3 - EISA 32 Bit Slave Signal Connections Table 10.1 - 208 Pin QFP Package Parameters Table 10.2 - 208 Pin TQFP Package Outlines Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 4 DATASHEET SMSC LAN91C100FD Rev. D ...
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... Switched Full Duplex, and the TCR bit enabling it is designated as SWFDUP. When the LAN91C100FD is configured for SWFDUP, it’s transmit and receive paths will operate independently and some CSMA/CD functions will be disabled. When the controller is not configured for SWFDUP it will follow the CSMA/CD protocol. SMSC LAN91C100FD Rev. D Page 5 DATASHEET Revision 1.0 (09-22-08) ...
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... D23 GND 122 D24 121 GND 120 VDD 119 D25 118 D26 117 GND 116 D27 115 D28 114 D29 113 D30 112 GND 111 D31 110 nRDYRTN 109 nLDEV 108 VDD 107 nSRDY 106 LCLK 105 SMSC LAN91C100FD Rev. D ...
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... Write/ W/nR nRead 181 nVL Bus nVLBUS Access 105 Local Bus LCLK Clock SMSC LAN91C100FD Rev. D BUFFER DESCRIPTION TYPE I Input. Decoded by LAN91C100FD to determine access to its registers. I Input. Used by LAN91C100FD for internal register selection. I Input. Used as an address qualifier. Address decoding is only enabled when AEN is low. ...
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... Input. Connected to the DO output of the serial pulldown EEPROM. I with Input. External switches can be connected to pullup these lines to select between predefined EEPROM configurations. I with Input. Enables (when high or open) pullup LAN91C100FD accesses to the serial EEPROM. Must be grounded if no EEPROM is connected to the LAN91C100FD. Page 8 DATASHEET SMSC LAN91C100FD Rev. D ...
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... Analog AGND Ground 2 Transmit TXEN Enable SMSC LAN91C100FD Rev. D BUFFER DESCRIPTION TYPE I/O4 with Bidirectional. Carries the local buffer memory pullups read and write data. Reads are always 32 bits wide. Writes are controlled individually at the byte level. Floated if FLTST=1 during RECEIVE ...
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... I with Input. Transmit clock input from MII. Nibble rate pullup clock (25 MHz). This pin is ignored when MIISEL is low. I with Input. Receive clock input from MII PHY. Nibble pullup rate clock. This pin is ignored when MIISEL is low. Page 10 DATASHEET SMSC LAN91C100FD Rev. D ...
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... O16 Output buffer with 8mA source and 16mA sink O24 Output buffer with 12mA source and 24mA sink OD16 Open drain buffer with 16mA sink SMSC LAN91C100FD Rev. D BUFFER DESCRIPTION TYPE I Inputs. Received Data nibble from MII PHY. These pins are ignored when MIISEL is low. ...
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... RCVDMA, RDMAH XTAL1, XTAL2 VDD, AVDD GND, AGND TXEN, TXD, CRS, COL, RXD, TXC, RXC, LBK, nLNK, nFSTEP, AUISEL, MIISEL TXEN100, CRS100, COL100, RX_DV, RX_ER, TXD0-TXD3, RXD0-RXD3, MDI, MDO, MCLK TX25, RX25 nCSOUT, nRXDISC Page 12 DATASHEET NUMBER OF PINS 205 SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability SERIAL EEPROM Address BUS Data INTERFACE UNIT Control RD WR FIFO FIFO SMSC LAN91C100FD Rev. D ARBITER DIRECT MEMORY ACCESS MEMORY MANAGEMENT UNIT RAM 25 MHz Figure 3.1 - LAN91C100FD Block Diagram Page 13 DATASHEET 10 Mb Interface MEDIA ...
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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability SERIAL EEPROM 1O Mbps LAN91C100FD FEAST MII OE,WE RD0-31 OR SRAM 3 4 32kx8 2 1 Page 14 DATASHEET LAN83C69 10BASE-T 10BASE-T INTERFACE 100BASE-T4 INTERFACE CHIP 100BASE-T4 100BASE-TX 100BASE-TX/ INTERFACE 10BASE-T LOGIC/ 10BASE-T SMSC LAN91C100FD Rev. D ...
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... The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement. The external memory used is a 25ns SRAM. SMSC LAN91C100FD Rev. D Page 15 DATASHEET ...
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... A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first out of the EPH Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 16 DATASHEET SMSC LAN91C100FD Rev. D ...
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... A write operation is also implemented by this block, that under CPU command will program specific locations in the EEPROM. This block is an autonomous state machine and controls the internal Data Bus of the LAN91C100FD during active operation. SMSC LAN91C100FD Rev. D Page 17 DATASHEET ...
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... Figure 4.1 - LAN91C100FD Internal Bock Diagram with Data Path Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability RX TX FIFO DMA FIFO TX COMPL FIFO ARBITER READ DATA REG MMU DATA ADDRESS BUFFER RAM Page 18 DATASHEET TRANSMIT RECEIVE CSMA/CD SMSC LAN91C100FD Rev. D ...
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... BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WORD, the BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of the last word is relevant. SMSC LAN91C100FD Rev. D STATUS reserved BYTE ...
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... This word is written at the beginning of each receive frame in memory not available as a register. HIGH ALGN BROD ERR BYTE CAST LOW BYTE 5 Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability ODD CRC 0 0 ODD BAD ODD TOOLNG CRC FRM HASH VALUE Page 20 DATASHEET TOO SHORT MULT CAST 1 0 SMSC LAN91C100FD Rev. D ...
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... Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, all registers can be accessed as doublewords, words or bytes. SMSC LAN91C100FD Rev. D HASH VALUE 5-0 000 000 ...
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... BASE PNR ARR IA0-1 FIFO PORTS IA2-3 POINTER IA4-5 DATA GENERAL PURPOSE DATA CONTROL INTERRUPT BANK SELECT BANK SELECT TYPE READ/WRITE Page 22 DATASHEET BANK3 MT0-1 MT2-3 MT4-5 MT6-7 MGMT REVISION RCV BANK SELECT SYMBOL BSR BS2 BS1 BS0 SMSC LAN91C100FD Rev. D ...
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... LAN91C100FD will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting result of FORCOL, will reset TXENA order to force another collision, TXENA must be set to 1 again. SMSC LAN91C100FD Rev. D NAME TYPE READ/WRITE ...
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... This bit is cleared by setting TXENA high. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ ONLY 0 CTR EXC _ROL _DEF SQET 16COL LTX MULT Page 24 DATASHEET SYMBOL EPHSR LOST LATCOL 0 CARR MUL SNGL TX_SUC COL COL SMSC LAN91C100FD Rev. D ...
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... PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission unless Full Duplex! RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The frame will not be received. The bit is cleared by RESET or by the CPU writing it low. SMSC LAN91C100FD Rev. D NAME TYPE READ/WRITE ...
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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ ONLY NUMBER OF DEFFERED SINGLE COLLISION COUNT NAME TYPE READ ONLY REGISTER FREE MEMORY AVAILABLE (IN BYTES * 256 * MEMORY SIZE (IN BYTES *256 * Page 26 DATASHEET SYMBOL ECR SYMBOL MIR SMSC LAN91C100FD Rev. D ...
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... NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three clocks on any cycle to the LAN91C100FD. SMSC LAN91C100FD Rev. D NAME TYPE Lower Byte - READ/WRITE ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability INTERRUPT PIN INT SEL0 NAME READ/WRITE A13 Reserved NAME READ/WRITE REGISTERS Page 28 DATASHEET USED INTR0 INTR1 INTR2 INTR3 TYPE SYMBOL BAR The I/O base decode defaults to 300h TYPE SYMBOL IAR SMSC LAN91C100FD Rev. D ...
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... This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C100FD. BANK 1 OFFSET C CONTROL REGISTER HIGH 0 RCV_ BAD BYTE 0 0 LOW LE CR BYTE ENABLE ENABLE 0 0 SMSC LAN91C100FD Rev. D ADDRESS ADDRESS ADDRESS ADDRESS ...
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... MMU COMMAND This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE WRITE ONLY REGISTER BUSY Bit Readable Page 30 DATASHEET SYMBOL MMUCR SMSC LAN91C100FD Rev. D ...
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... TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. SMSC LAN91C100FD Rev Page 31 DATASHEET ...
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... Poll ALLOC_INT bit until set 3. Read Allocation Result Register Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ/WRITE PACKET NUMBER AT TX AREA NAME TYPE READ ONLY ALLOCATED PACKET NUMBER Page 32 DATASHEET SYMBOL PNR SYMBOL ARR SMSC LAN91C100FD Rev. D ...
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... When RCV is set the address refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address refers to the transmit area and uses the packet number at the Packet Number Register. SMSC LAN91C100FD Rev. D NAME TYPE ...
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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability NAME DATA REGISTER READ/WRITE DATA HIGH DATA LOW NAME READ ONLY RX_OVRN ALLOC INT INT Page 34 DATASHEET TYPE SYMBOL DATA TYPE SYMBOL IST TX EMPTY TX INT RCV INT INT SMSC LAN91C100FD Rev. D ...
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... EPH INT will only be cleared by the following methods: 1. Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK transition. 2. Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over. SMSC LAN91C100FD Rev. D NAME WRITE ONLY REGISTER RX_OVRN INT ...
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... FIFO PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register. The Receive Interrupt is cleared when RX FIFO is empty. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 36 DATASHEET SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC LAN91C100FD Rev. D Figure 5.2 - Interrupt Structure Page 37 DATASHEET Revision 1.0 (09-22-08) ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE READ/WRITE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE MULTICAST TABLE NAME TYPE READ/WRITE MDOE Page 38 DATASHEET SYMBOL SYMBOL MGMT MCLK MDI MDO 0 MDI Pin 0 SMSC LAN91C100FD Rev. D ...
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... When set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register. RCV DISCRD is self clearing. MBO – Must be 1. SMSC LAN91C100FD Rev. D NAME TYPE READ ONLY ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability NAME TYPE EXTERNAL R/W REGISTER EXTERNAL R/W REGISTER NCSOUT Driven low. Transparently latched on nADS rising edge. High High Page 40 DATASHEET SYMBOL LAN91C100FD DATA BUS Ignored on writes. Tri-stated on reads. Ignore cycle. Normal LAN91C100FD cycle. SMSC LAN91C100FD Rev. D ...
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... EPH STATUS Register, write the packet number of the current packet to the Packet Number Register, re-enable TXENA, then go to step 4 to start the TX sequence again. SMSC LAN91C100FD Rev. D MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... Transmit pages are released by transmit completion. a) The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets failure occurs on any packets, TX INT is generated and TXENA is cleared, transmission sequence stops. The packet number of the failure packet is presented at the TX FIFO PORTS Register. Page 42 DATASHEET SMSC LAN91C100FD Rev. D ...
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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC LAN91C100FD Rev. D MAC SIDE A packet is received with matching address. Memory is requested from MMU. A packet number is assigned to it. Additional memory is requested if more pages are needed ...
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... Figure 5.3 - Interrupt Service Routine Page 44 DATASHEET Yes RX INTR? Call RXINTR Write Allocated Pkt # into Packet Number Reg. Write Ad Ptr Reg. & Copy Data & Source Address Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Disable Allocation Interrupt Mask SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability SMSC LAN91C100FD Rev INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Yes No Destination Multicast? Read Words from RAM for Address Filtering Address No Yes Filtering Pass? No Yes Status Word OK? Do Receive Lookahead Get Copy Specs from Upper ...
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... Write Address Pointer Register Read Status Word from RAM Yes TX Status No OK? Immediately Issue "Release" Command Update Variables Acknowledge TXINTR Read TX INT Again No TX INT = 0? Yes Restore Packet Number Return to ISR Figure 5 INTR Page 46 DATASHEET Update Statistics Re-Enable TXENA SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) SMSC LAN91C100FD Rev. D TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = X & ...
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... Packet # Register into RAM Write Source Address into Proper Location Copy Remaining TX Data Packet into RAM Enqueue Packet Set "Ready for Packet" Flag Return Page 48 DATASHEET No Store Data Buffer Pointer Clear "Ready for Packet" Flag Enable Allocation Interrupt SMSC LAN91C100FD Rev. D ...
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... Depending on the completion code the driver will take different actions. Note that the transmit process is working in parallel and other transmissions might be taking place. The LAN91C100FD is virtually queuing the packet numbers and their status words. SMSC LAN91C100FD Rev. D Page 49 DATASHEET Revision 1.0 (09-22-08) ...
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... Transmit Status reading (interrupt driven). 1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability Page 50 DATASHEET SMSC LAN91C100FD Rev. D ...
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... TX EMPTY TWO INT OPTIONS TX INT ALLOC INT 'NOT EMPTY' PACKET NUMBER M.S. BIT ONLY Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU SMSC LAN91C100FD Rev. D PACKET NUMBER REGISTER 'EMPTY' TX DONE CPU ADDRESS PACK # OUT Page 51 DATASHEET 'NOT EMPTY' RX FIFO PACKET NUMBER ...
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... On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability REGISTER EEPROM WORD ADDRESS IOS Value * 4 (IOS Value * Page 52 DATASHEET SMSC LAN91C100FD Rev. D ...
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... If no EEPROM is connected to the LAN91C100FD, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value. SMSC LAN91C100FD Rev. D Page 53 DATASHEET This ...
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... CONFIGURATION REG. 9h BASE REG. Ch CONFIGURATION REG. Dh BASE REG. 10h CONFIGURATION REG. 11h BASE REG. 14h CONFIGURATION REG. 15h BASE REG. 18h CONFIGURATION REG. 19h BASE REG. 20h 21h 22h Figure 6 Serial EEPROM Map Page 54 DATASHEET 16 BITS IA0-1 IA2-3 IA4-5 SMSC LAN91C100FD Rev. D ...
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... RESET nBE0 nBE1 nBE0 nBE1 nBE2 nBE3 nBE2 nBE3 SMSC LAN91C100FD Rev. D NOTES Address bus used for I/O space and register decoding, latched by nADS rising edge, and transparent on nADS low time. Qualifies valid I/O decoding - enabled access when low. This signal is latched by nADS rising edge and transparent on nADS low time ...
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... Byte 3 access Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. nLDEV is a totem pole output. nLDEV is active on valid decodes of A15-A4 and AEN=0. UNUSED PINS Page 56 DATASHEET SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability VL BUS W/nR A2-A15 LCLK M/nIO nRESET IRQn D0-D31 nRDYRTN nBE0-nBE3 nADS delay 1 LCLK nLRDY nLDEV SMSC LAN91C100FD Rev. D W/nR A2-A15 LCLK AEN RESET LAN91C100FD INTR0-INTR3 D0-D31 nRDYRTN nBE0-nBE3 nADS nCYCLE nSRDY O.C. simulated O ...
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... Lower Not used 1 0 Not used Upper Not used = tri-state on reads, ignored on writes nLDEV is a totem pole output. Must be buffered using an open collector driver. nLDEV is active on valid decodes of A15-A4 and AEN=0. UNUSED PINS No upper word access. Page 58 DATASHEET SMSC LAN91C100FD Rev. D ...
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... FEAST Fast Ethernet Controller with Full Duplex Capability ISA BUS A1-A15, AEN RESET VCC D0-D15 nIRQ nIORD nIOWR A0 nSBHE nIOCS16 SMSC LAN91C100FD Rev. D A1-A15, AEN RESET nBE2, nBE3 D0-D15 LAN91C100FD INTR0-INTR3 nRD nWR nBE0 nBE1 nLDEV O.C. Figure 7.2 - LAN91C100FD on ISA Bus ...
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... Byte 3 access Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application. Other combinations of nBE are not supported by the LAN91C100FD. Software drivers are not anticipated to generate them. Page 60 DATASHEET SMSC LAN91C100FD Rev. D ...
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... VCC nVLBUS GND A1 SMSC LAN91C100FD Rev. D NOTES nLDEV is a totem pole output. nLDEV is active on valid decodes of LAN91C100FD pins A15-A4, and AEN=0. nNOWS is similar to nLDEV except that it should go inactive on nSTART rising. nNOWS can be used to request compressed cycles (1.5 BCLK long, nRD/nWR will be 1/2 BCLK wide) ...
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... LATCH + gates nWR BCLK nSTART nEX32 Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability A2-A15 RESET AEN D0-D31 INTR0-INTR3 LAN91C100FD nBE0-nBE3 nRD nWR LCLK nADS nLDEV O.C. Figure 7.3 - LAN91C100FD on EISA Bus Page 62 DATASHEET SMSC LAN91C100FD Rev. D ...
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... I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Low Input Level High Input Level Schmitt Trigger Hysteresis I Input Buffer CLK Low Input Level High Input Level SMSC LAN91C100FD Rev. D SYMBOL MIN TYP MAX V 0.8 ILI 2.0 V IHI V ...
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... Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability SYMBOL MIN TYP MAX I -10 + -10 + -150 - +75 +150 - - - - -10 +10 OL Page 64 DATASHEET UNITS COMMENTS µ µ µ µ µ µ µ SMSC LAN91C100FD Rev. D ...
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... Low Output Level High Output Level Output Leakage Supply Current Active CAPACITANCE 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CAPACITIVE LOAD ON OUTPUTS nARDY, D0-D31 (non VLBUS) D0-D31 in VLBUS All other outputs SMSC LAN91C100FD Rev. D SYMBOL MIN TYP MAX V 0 +10 - ...
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... High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability A1-15, AEN, nBE0-nBE3 valid t3 t1 D0-D31 valid PARAMETER Page 66 DATASHEET t5A MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...
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... Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive t8 A1-A15, AEN, nBE0-nBE3 Setup to nADS Rising t9 A1-A15, AEN, nBE0-nBE3 Hold after nADS Rising SMSC LAN91C100FD Rev D0-D31 valid PARAMETER Page 67 DATASHEET t4 t5A MIN ...
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... Low to Valid Data t4 nRD High to Data Floating t5 Data Setup to nWR Inactive t5A Data Hold After nWR Inactive Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t3 t1 D0-D31 valid PARAMETER Page 68 DATASHEET t5A MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...
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... Setup to LCLK Falling t15 nRDYRTN Hold after LCLK Falling t17 nCYCLE High and W/nR High Overlap t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) SMSC LAN91C100FD Rev. D t12 t17 t20 t18 a b PARAMETER Page 69 DATASHEET ...
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... Data Delay from LCLK Rising (Read) Note 9.1 (holdt.) Note 9.2 (Setupt.) Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t12 t17 t19 a b t15 t14 MIN TYP (Note 9.1) Page 70 DATASHEET t13 c t17 MAX UNITS (Note 9.2) SMSC LAN91C100FD Rev. D ...
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... W/nR Setup to nCYCLE Active t17A W/nR Hold after LCLK Rising with nLRDY Active t18 Data Setup to LCLK Rising (Write) t20 Data Hold from LCLK Rising (Write) t21 nLRDY Delay from LCLK Rising SMSC LAN91C100FD Rev A1-A15, AEN, nBE0-nBE3 t25 MIN t9 A1-A15, AEN, nBE0-nBE3 t8 t16 ...
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... Setup to LCLK Rising t24 nRDYRTN Hold after LCLK Rising Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t9 A1-A15, AEN, nBE0-nBE3 t8 t10 t16 t11 PARAMETER Page 72 DATASHEET t23 t24 D0-D31 t21 t21 MIN TYP MAX UNITS SMSC LAN91C100FD Rev. D ...
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... Write – RD0-RD31 Hold after nRWE0-nRWE3 Rising t39 Write – nRWE0-nRWE3 Pulse Width t54 Write – RA2-RA16 Valid to End of Write t38 Read – RA2-RA16 Valid to RD0-RD31 Valid t51 Read – RD0-RD31 Hold after RA2-RA16 Change SMSC LAN91C100FD Rev. D t50 t50 t54 t35 t38 t39 t39 t36 ...
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... RXC starts after CRS goes active. RXC stops after CRS goes inactive. 3. COL is an asynchronous input. Revision 1.0 (09-22-08) FEAST Fast Ethernet Controller with Full Duplex Capability t30 Figure 9.10 - ENDEC Interface - 10 Mbps MIN TYP Page 74 DATASHEET MIN TYP MAX UNITS t31 t32 MAX UNITS SMSC LAN91C100FD Rev. D ...
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... RX25 RX_DV RX_ER PARAMETER t27 TXD0-TXD3, TXEN100 Delay from TX25 Rising t28 RXD0-RXD3, RX_DV, RX_ER Setup to RX25 Rising t29 RXD0-RXD3, RX_DV, RX_ER Hold After RX25 Rising SMSC LAN91C100FD Rev. D t27 t27 Figure 9.11 - MII Interface MIN Page 75 DATASHEET t28 t28 t28 ...
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... X Body Size 30.85 Y Span 28.10 Y body Size 0.20 Lead Frame Thickness 0.75 Lead Foot Length ~ Lead Length Lead Pitch o 7 Lead Foot Angle 0.30 Lead Width ~ Lead Shoulder Radius 0.25 Lead Foot Radius 0.08 Coplanarity Page 76 DATASHEET SMSC LAN91C100FD Rev. D ...
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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LAN91C100FD Rev. D MAX REMARK 1.60 Overall Package Height 0.15 Standoff 1 ...