PX1011A-EL1/G NXP Semiconductors, PX1011A-EL1/G Datasheet - Page 20

Telecom Line Management ICs PCI EXPRESS STAND ALONE X1 PHY

PX1011A-EL1/G

Manufacturer Part Number
PX1011A-EL1/G
Description
Telecom Line Management ICs PCI EXPRESS STAND ALONE X1 PHY
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PX1011A-EL1/G

Product
PHY
Supply Voltage (max)
1.25 V, 3.6 V
Supply Voltage (min)
1.15 V, 1.2 V
Supply Current
0.025 A
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Channels
1
Package / Case
LFBGA-81
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PX1011A-EL1/G,557

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PX1011A-EL1/G
Manufacturer:
KEC
Quantity:
15 562
Part Number:
PX1011A-EL1/G,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
PX1011A-EL1/G,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
11. Characteristics
Table 18.
PX1011A_PX1012A_2
Product data sheet
Symbol
Supplies
V
V
V
V
V
V
I
I
I
I
I
I
Receiver
UI
V
t
V
Z
Z
RL
RL
f
f
V
V
t
t
t
DDD1
DDD2
DDD3
DD
DDA1
DDA2
RX_MAX_JITTER
clk(ref)
mod(clk)(ref)
lock(CDR)(ref)
lock(CDR)(data)
RX_latency
RX_DC
RX_HIGH_IMP_DC
f
DDD1
DDD2
DDD3
DD
DDA1
DDA2
RX_DIFFp-p
IDLE_DET_DIFFp-p
IH(se)REFCLK
IL(se)REFCLK
mod(clk)(ref)
RX_DIFF
RX_CM
PCI Express PHY characteristics
Parameter
digital supply voltage 1
digital supply voltage 2
digital supply voltage 3
supply voltage
analog supply voltage 1
analog supply voltage 2
digital supply current 1
digital supply current 2
digital supply current 3
supply current
analog supply current 1
analog supply current 2
unit interval
differential input peak-to-peak voltage
maximum receiver jitter time
electrical idle detect threshold
DC input impedance
powered-down DC input impedance
differential return loss
common mode return loss
reference clock frequency
reference clock modulation frequency range
reference clock modulation frequency
REFCLK single-end HIGH-level input voltage
REFCLK single-end LOW-level input voltage
CDR lock time (reference loop)
CDR lock time (data loop)
receiver latency
Rev. 02 — 18 May 2006
Conditions
for JTAG I/O
for SSTL_2
I/O
for core
for high-speed
serial I/O and
PVT
for serializer
for serializer
for I/O
for SSTL_2;
no load
for core
for high-speed
serial I/O and
PVT
for serializer
for serializer
1 clock cycle
is 4 ns
PX1011A/PX1012A
PCI Express stand-alone X1 PHY
Min
3.0
2.3
1.2
1.15
1.2
3.0
0.1
10
5
15
15
7
399.88 400
0.175
-
65
40
200
15
6
99.97
30
-
-
-
-
6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
0.5
Typ
3.3
2.5
1.25
1.2
1.25
3.3
1
18
10
20
20
10
-
-
-
50
-
-
-
100
-
-
0.7
0
-
-
-
Max
3.6
2.7
1.3
1.25
1.3
3.6
2
25
15
25
25
15
400.12 ps
1.2
0.6
175
60
-
-
-
100.03 MHz
+0
33
-
-
50
2.5
13
Unit
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
V
UI
mV
k
dB
dB
%
kHz
V
V
clock
cycle
20 of 32
s
s

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