LX256EB-5F484C Lattice, LX256EB-5F484C Datasheet - Page 43
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LX256EB-5F484C
Manufacturer Part Number
LX256EB-5F484C
Description
Analog & Digital Crosspoint ICs E-Series, 256 I/O Switch Matrix, 2.5V, 5ns
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX256EB-5F484C
Maximum Dual Supply Voltage
2.7 V
Minimum Dual Supply Voltage
2.3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V
Supply Type
Triple
Configuration
256 x 256
Package / Case
FPBGA-484
Data Rate
38 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
LOCKIN Time
REFCLK and SS_CLKIN Timing
Serializer Timing
t
t
t
t
t
t
t
t
t
t
1. REFCLK clock period.
t
t
t
t
t
t
t
t
1. Bt: Bit Time Period. High Speed Serial Bit Time.
2. The SIN and SOUT jitter specifications listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
3. Internal timing for reference only.
DREFCLK
JPPREFCLK
PWREFCLK
RFREFCLK
SCLOCK
CDRLOCK
SYNC
CAL
SUSYNC
HDSYNC
JPPSOUT
JPP8B10B
RFSOUT
COSOUT
SKTX
CKOSOUT
HSITXDDATAS
HSITXDDATAH
Symbol
sysCLOCK PLL BYPASS mode.
Symbol
Symbol
SOUT Peak-to-Peak Output Data Jitter
SOUT Peak-to-Peak Random Jitter
SOUT Peak-to-Peak Deterministic Jitter
SOUT Output Data Rise/Fall Time (20%,
80%)
REFCLK to SOUT Delay
Skew of SOUT with Respect to
SS_CLKOUT
SS_CLKOUT to bit0 of SOUT
TXD Data Setup Time
TXD Data Hold Time
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or
80% to 20%)
CSPLL Lock Time
CDRPLL Lock-in Time
SyncPat Length
CAL Duration
SyncPat Set-up Time to CAL
SyncPat Hold Time from CAL
2
Description
Description
Description
10B12B
8B10B
Mode
SS/8B10B
SS
SS
SS
SS
SS
All
10B12B
BLVDS
8B10B
8B10B
Mode
LVDS
SS
SS
All
All
All
40
After input is stabilized
With SS mode sync pattern
With 10B12B sync pattern
With 8B10B idle pattern
f
800 Mbps w/K28.7-
800 Mbps w/K28.5+
Note 3
Note 3
CLK
10B12B
8B10B/
Mode
with no jitter
All
All
All
Condition
Condition
Random Jitter
Condition
ispGDX2 Family Data Sheet
2Bt
2Bt
1Bt
1
Min.
1.5
- t
1
1
+ 2
+ 2
SKTX
1200
1100
Min.
Min.
-100
50
50
1
2Bt
2Bt
1Bt
1
Max.
0.25
130
160
700
900
250
1.0
+ t
1
1
Max.
1024
1024
Max.
0.01
960
+10
+10
100
25
SKTX
2
Units
Units
Units
UIPP
t
UIPP
t
t
t
t
t
t
ppm
RCP
RCP
RCP
RCP
RCP
RCP
RCP
μS
ps
ps
ps
ps
ns
ns
ps
ns
ns
ns
ns
ns
1