COM20019ILJPTR SMSC, COM20019ILJPTR Datasheet - Page 8

• Manufacturer Part Number: COM20019ILJPTR
• Description: Network Controller & Processor ICs Arcnet (ANSI 878.1) Controllr 2k x 8 Ram
• Manufacturer: SMSC

Specifications of COM20019ILJPTR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3
Rev. 09-25-07
PLCC PIN
4-6,8-12
NO.
1-3
27
26
23
24
25
Address
0-2
Data 0-7
nRead/nData
Strobe
nWrite/
Direction
nReset in
nInterrupt
nChip Select
DESCRIPTION OF PIN FUNCTIONS
NAME
MICROCONTROLLER INTERFACE
nINTR
nCS
A0/nMUX,
A1,A2/ALE
AD0-AD2, D3-
D7
nRD/nDS
nWR/DIR
nRESET
SYMBOL
DATASHEET
Page 8
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Input. On a non-multiplexed mode, A0-A2 are
address input bits. (A0 is the LSB) On a
multiplexed address/data bus, nMUX tied Low,
A1 is left open, and ALE is tied to the Address
Latch Enable signal. A1 is connected to an
internal pull-up resistor.
Input/Output. On a non-multiplexed bus, these
signals are used as the data lines for the
device. On a multiplexed address/data bus,
AD0-AD2 act as the address lines (latched by
ALE) and as the low data lines for the device.
D3-D7 are always used for data only. These
signals are connected to internal pull-up
resistors.
Input. On a 68XX-like bus, nDS is an active
low signal issued by the microcontroller as the
data strobe signal to strobe the data onto the
bus. On a 80XX-like bus, nRD is an active low
signal issued by the microcontroller to indicate
a read operation.
Input. On a 68XX-like bus, DIR is issued by
the microcontroller as the Read/nWrite signal
to determine the direction of data transfer. In
this case, a logic "1" selects a read operation,
while a logic "0" selects a write operation. In
this case, data is actually strobed by the nDS
signal. On an 80XX-like bus, nWR is an active
low signal issued by the microcontroller to
indicate a write operation. In this case, a logic
"0" on this pin, when the COM20019I is
accessed, enables data from the data bus to
be written to the device.
Input. This active low signal executes a
hardware reset.
Output. This active low signal is generated by
the COM20019I when an enabled interrupt
condition occurs.
Input. This active low signal selects the
COM20019I for an access.
DESCRIPTION
SMSC COM20019I