LX128B-32FN208C Lattice, LX128B-32FN208C Datasheet - Page 33
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LX128B-32FN208C
Manufacturer Part Number
LX128B-32FN208C
Description
Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 2.5V, SERDES, 3.2ns, Pb-Free
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX128B-32FN208C
Maximum Dual Supply Voltage
2.7 V
Minimum Dual Supply Voltage
2.3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V
Supply Type
Triple
Configuration
128 x 128
Package / Case
FPBGA-208
Data Rate
21 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)
Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)
(Global RESET)
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
(I/O RESET)
(SSCLKIN)
(REFCLK)
(Control)
(SIN)
t
t
t
HSICTRLCAL
HSISSCLKIN
HSIREFCLK
t
HSISIN
t
HSIFIFORST
from I/O Cell
from I/O Cell
(REFCLK)
HSI Controls
(TXD)
Serial Data
In
CAL
Source
Synchronous Clock
Reference Clock
sysHSI
(RXD)
RESET
t
t
HSITXDATA
HSIREFCLK
HSI Flags
Recovered
CSLOCK
Data Out
(RXD)
SYDT
Clock
Data In
Reference Clock
from I/O Cell
from I/O Cell
(RCLK)
(RE)
(Output Path Flag)
(SYDT and Output
Path Flags)
to I/O Cell
to I/O Cell
30
t
t
FIFODATAIN
FIFOWCLK
sysHSI
(TXD)
Synchronous Clock
t
t
FIFORCLK
FIFOREN
Data Out
Source
Serial
Write CLK
Read
Clock
Read
Enable
Data In
RESET
ispGDX2 Family Data Sheet
FIFO
to I/O Cell
(SSCLKOUT)
(SOUT)
to I/O Cell
FULL, EMPTY
FIFO Flags
Data Out
(Output Path Flags)
(RECCLK)
to I/O Cell
to I/O Cell
(DOUT)
to I/O Cell