COM20019ILJP SMSC, COM20019ILJP Datasheet - Page 67

• Manufacturer Part Number: COM20019ILJP
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20019ILJP

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 312.5 Kbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up
register. The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not
synchronized between the CPU and COM20019I 3V. Thus, changing the CKP3-1 timing does not
synchronize with the internal clocks of Pre-Scalar, and changing CKP3-1 may cause spike noise to appear
on the output clock line.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for
synchronizing the CKP3-1 with Pre-Scalar’s internal clocks.
C) Shorten The Write Interval Time To The Command Register
The COM20019I 3V limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 800 nS at the 312.5 Kbps and 1.6 μ S at the
156.25 Kbps. This 1.6 μ S is very long for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL
clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20019I 3V has a write prohibition period for writing the Enable Transmit/Receive Commands.
This period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused
by setting the TA/RI bit with a pulse signal. It is 3.2 μ S at 156.25 Kbps. This period may be a problem
when using interrupt processing. The interrupt occurs when the RI bit returns to High. The CPU writes the
next Enable Receive Command to the other page immediately. In this case, the interval time between the
interrupt and writing Command is shorter than 3.2 μ S.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the
TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1.
EF=0
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
prohibition period
EF=1
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT
SMSC COM20019I 3.3V
Page 67
Rev. 11-07-08
DATASHEET