UPB1009K NEC, UPB1009K Datasheet - Page 14

• Manufacturer Part Number: UPB1009K
• Description: Telecom ICs RO 551-UPB1009K-A
• Manufacturer: NEC

Specifications of UPB1009K

• Mounting Style: SMD/SMT
• Package / Case: QFN-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL
1 4
<PLL Synthesizer>
Circuit Current 4
Charge Pump Output Current
Loop Filer Output (High Level)
Loop Filer Output (Low Level)
Reference Input Level
VCO Modulation Sensitivity
VCO Control Voltage
C/N
<A/D Converter>
Circuit Current 5
Resolution
Sampling Clock
Input Band Width
Integral Non-linear Error
Signal-to-noise Ratio
Signal-to-noise + Distortion Ratio
Number
Total Harmonic Distortion Ratio
Remarks 1. Timing characteristics of ADC during normal operation
Parameter
A buffer amplifier is internally inserted before the ADC core of the µ PB1009K. The bias of this buffer amplifier
is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC.
Because the ladder resistor of the ADC is directly connected between V
V
DD
ana affect the resolution of the ADC.
CHARACTERISTICS (T
Symbol
I
ResAD
ADBW
SINAD
ENOB
cpsource
I
V
SNR
THD
C/N
cpsink
I
I
INL
KV
VT
CC4
REFin
CC5
fs
PLL, VCO current, MS1 = L, MS2 = L
V
Center frequency
When PLL is Locked
Δ 10 kHz
DC characteristics
IF = 5.17 MHz, fs = 20.48 MHz
IF = 5.17 MHz, fs = 20.48 MHz
ENOB = (SINAD−1.763)/6.02
IF = 5.17 MHz, fs = 20.48 MHz
Second-degree to fifth-degree distortion
components
13 pin
= V
A
CC
/2
= +25°C, V
Test Conditions
C C
= 3.0 V)
V
MIN.
−0.55
CC
0.35
70.0
22.0
20.0
8.0
0.5
3.1
5.1
3.0
−0.3
−
−
−
−
−
−
−
DD
ana and GNDana, changes in
TYP.
−0.45
0.45
81.0
25.3
25.1
100
−40
9.5
0.2
1.3
4.1
0.2
3.9
−
−
4
−
−
MAX.
−0.35
10.6
0.55
−30
0.2
1.6
2.0
5.4
1.0
20
−
−
−
−
−
−
−
−
UPB1009K
dBc/Hz
MHz
MHz
MHz
Unit
LSB
mA
mA
mA
mA
bits
bits
dBc
V
dB
dB
V
V
V
PP