SI2401-FSR Silicon Laboratories Inc, SI2401-FSR Datasheet - Page 57

• Manufacturer Part Number: SI2401-FSR
• Description: Telecom Line Management ICs 2400b/s System Side 3rd Gen DAA Tech
• Manufacturer: Silicon Laboratories Inc
• Type: Integrated Global DAAr

Specifications of SI2401-FSR

• Product: Modem Module
• Supply Voltage (min): 3 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SEE (RVC3). Ring Validation Control 3
Reset settings = 0001_0110 (0x16)
Bit
7:4
3:0
Name
Type
Bit
RMX[3:0]
RTO[3:0]
Name
D7
Ring Timeout.
These bits set when a ring signal is determined to be over after the most recent ring
threshold crossing.
RTO[3:0]
0000
0001
0010
.
.
.
1111
Ring Assertion Maximum Count.
These bits set the maximum ring frequency for a valid ring signal. During ring qualification,
a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-
ular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the
RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too
high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies
the minimum duration between TIP/RING events to qualify as a ring, in binary-coded incre-
ments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period.
At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the cor-
rect RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be
used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)).
D6
RTO[3:0]
R/W
Ring Timeout
1920
80
128
256
D5
m
m
m
s
m
s
s
s
Rev. 1.1
D4
Function
D3
D2
Si2401/Si3008
RMX[3:0]
R/W
D1
D0
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