PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet
PSB21384HV1.3
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PSB21384HV1.3 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... BCL edge changed to ’falling’ edge 245 Figure 95 modified 250 Timings added 251 251 Power supply currents added For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com 2001-03-12 09. ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.3.6 Data Transfer and Delay between IOM and S/T Interface . . . . . . . . . . . 76 2.3.7 Control of Layer ...
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Table of Contents 4.2.1 Transmit Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 7 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 ...
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Table of Contents 7.3.4 CO_CR - Control Register Codec Data . . . . . . . . . . . . . . . . . . . . . . . . .212 7.3.5 TR_CR - Control Register ...
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Table of Contents 8.1.7.2 Parallel Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . .248 8.1.8 Reset . . . . . . . . ...
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Overview The SCOUT-S or SCOUT-SX respectively integrates all necessary functions for the completion of a cost effective ISDN voice terminal solution. Please note: Throughout the whole document “SCOUT and “SCOUT The SCOUT combines the functionality of the ARCOFI Codec ...
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Comparison of the SCOUT with the two chip solution ISAC-S TE and ARCOFI-BA; -SP Operating modes Supply voltage Technology Package Transceiver Transformer ratio for receiver and transmitter Test Functions Microcontroller Interface Microcontroller clock Register address space Codec CRAM access (128 ...
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Data control and manipulation IOM-2 IOM-2 Interface Monitor channel programming C/I channels Layer-1 statemachine Statemachine in software IDSL (144kBit/s) HDLC support FIFO size Reset Sources Codec Analog inputs Band gap reference Data Sheet SCOUT Various possibilities of data control and ...
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Max. AFE gain transmit (guaranteed transmission characteristics) Analog gain steps earpiece Speakerphone Status indication AGC initialization Voice data manipulation Voice data formats Mask register for voice data Provided Tone Generator Output Direct tone generator output to loudspeaker Saturation amplification of ...
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Siemens Codec with U SCOUT-S, SCOUT-SX Version 1.3 1.1 Features • 8-bit parallel microcontroller interface (only PSB 21382/4 in P-MQFP-64 package), Motorola, Siemens/Intel bus type multiplexed or non-multiplexed, direct-/indirect register addressing • Serial control interface (SCI) • IOM-2 interface in ...
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Activation and deactivation procedures with automatic activation from power down state • HDLC controller. Operating in non-auto mode, transparent mode 0-2 or extended transparent mode. Access to B1 channels or the combination of them e.g. for ...
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Pin Configuration VDDSEL reserved V DDA V SSA V REF BGREF AXI MIN2 MIP2 MIN1 MIP1 VDDSEL reserved 50 reserved DDA V 56 SSA2 V 57 SSA1 V 58 REF ...
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Logic Symbol P-MQFP REF BGREF AXI MIN1 MIP2 MIN2 HOP HON LSP LSN seperate power pins seperate ground pins SS P-MQFP ...
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Pin Definitions and Function Table 1 Pin No. Pin No. Symbol MQFP-44 MQFP- DDL 16 V DDD 25 V DDD1 8 V DDD2 DDA DDP DDPLL V ...
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Table 1 (cont’d) Pin No. Pin No. Symbol MQFP-44 MQFP- SDS1 10 15 RSTO/ SDS2 9 14 RST 32 47 SR1 33 48 SR2 28 43 SX1 29 44 SX2 13 18 XTAL2 14 19 XTAL1 15 20 ...
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Table 1 (cont’d) Pin No. Pin No. Symbol MQFP-44 MQFP- R SCLK 28 SCLK AD5 19 SDR 29 SDR AD6 20 30 SDX SDX AD7 - 21 AD0 22 AD1 23 AD2 24 ...
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Table 1 (cont’d) Pin No. Pin No. Symbol MQFP-44 MQFP- Data Sheet Input (I) Function Output (O) Open Drain (OD) I Multiplexed bus ...
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Table 1 (cont’d) Pin No. Pin No. Symbol MQFP-44 MQFP- REF 39 59 BGREF 40 60 AXI 44 64 MIP1 43 63 MIN1 42 62 MIP2 41 61 MIN2 5 5 HOP 6 6 HON 2 2 ...
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Typical Applications The SCOUT can be used in a variety of applications like • ISDN voice terminal (Figure 3) • ISDN voice terminal with speakerphone (Figure 4) • ISDN voice terminal as featurephone with acoustic echo cancellation (Figure 5) ...
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Figure 4 ISDN Voice Terminal with Speakerphone Figure 5 ISDN Voice Terminal as Featurephone with Acoustic Echo Cancellation Data Sheet SCOUT-SX SCI µC SCOUT-S IOM-2 SCI µC ACE 15 PSB 21381/2 PSB 21383/4 Overview S-Interface voice_te_s.vsd S-Interface vt_ace_s.vsd 2001-03-12 ...
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Fax Figure 6 ISDN Voice Terminal with Tip/Ring Extension SCI Figure 7 ISDN Voice Terminal with Answering Machine Data Sheet SCOUT-SX IOM-2 SLIC ARCOFI-BA SCOUT-SX IOM-2 Memory SAM Microcontroller 16 PSB 21381/2 PSB 21383/4 Overview S-Interface SCI µC vt_tipring_s.vsd S-Interface ...
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SCI Figure 8 ISDN Voice Terminal with Full Duplex Speakerphone and Answering Machine Video Figure 9 ISDN Videophone with Speakerphone Data Sheet SCOUT-S IOM-2 Memory SAM_EC Microcontroller SCOUT-SX IOM-2 Video JADE Codec Microcontroller 17 PSB 21381/2 PSB 21383/4 Overview S-Interface ...
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Video Figure 10 ISDN Videophone with Full Duplex Speakerphone Figure 11 ISDN Voice/Data Terminal Card Data Sheet SCOUT-S IOM-2 Video ACE JADE Codec Microcontroller SCOUT-SX IOM-2 ISAR Bus Interface 18 PSB 21381/2 PSB 21383/4 Overview S-Interface SCI ...
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SLIC Figure 12 ISDN Voice/Data Terminal with Tip/Ring Extension Fax Figure 13 Terminal Adapter with Dual Tip/Ring Data Sheet SCOUT-SX IOM-2 ARCOFI-BA Microcontroller V.24 Interface SCOUT-S SLIC IOM-2 SLIC ARCOFI-BA 19 PSB 21381/2 PSB 21383/4 Overview S-Interface ISAR vt_data_tipring_s.vsd S-Interface ...
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General Functions and Device Architecture Figure 14 shows the architecture of the SCOUT containing the following functional blocks: • S/T interface transceiver with ISAC-S TE PSB 2186 functionality respectively • Serial and parallel microcontroller interface • HDLC controller with ...
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Figure 14 Architecture of the SCOUT Data Sheet 21 PSB 21381/2 PSB 21383/4 Overview 2001-03-12 ...
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Interfaces The SCOUT provides the following interfaces: • Serial and 8-bit microcontroller interface together with a reset and microcontroller clock generation. • IOM-2 interface as an universal backplane for terminals • S/T interface towards the four wire subscriber line ...
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Microcontroller Interface Depending of the package the SCOUT supports a serial or a parallel microcontroller interface. In the P-MQFP-44 package only a serial interface is supported whereas in the P-MQFP-64 package either a serial or a parallel microcontroller interface ...
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The mapping of all accessible registers can be found in figure 92 in chapter 7. The microcontroller interface also consists of a microcontroller clock generation at pin MCLK and an interrupt request at pin INT. 2.1.1 Serial Control Interface (SCI) ...
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Figure 15 Serial Control Interface Timing Data Sheet 25 PSB 21381/2 PSB 21383/4 Interfaces 2001-03-12 ...
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Programming Sequences The principle structure of a read/write access to the SCOUT registers via the serial control interface is shown in figure 16. write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 16 Serial Command Structure ...
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Table 4 (cont’d) Header Byte Code Adr-Data-Data-Data Header 00 : ARCOFI Compatible Sequence H This programming sequence is compatible to the SOP, COP and XOP command sequences of the ARCOFI. ...
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Header Interleaved A-D-A-D Sequences H H The interleaved A-D-A-D sequences give direct read/write access to the address range 00 -6F (header the CRAM range have any length. This mode ...
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Header 43 : Read-/Write- only A-D-D-D Sequence H This mode (header 43 ) can be used for a fast access to the HDLC FIFO data. Any H address (rdadr, wradr) in the range between 00h and 1F gives access to ...
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Parallel Microcontroller Interface The 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. The parallel interface provides three types of P buses which are selected via pin ALE. The bus operation modes ...
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Figure 17 Direct/Indirect Register Address Mode Data Sheet 31 PSB 21381/2 PSB 21383/4 Interfaces 2001-03-12 ...
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Interrupt Structure and Logic Special events in the SCOUT are indicated by means of a single interrupt output, which requests the host to read status information from the SCOUT or transfer data from/to the SCOUT. Since only one INT ...
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Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller (HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow (WOV) ...
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Microcontroller Clock Generation The microcontroller clock is provided by the pin MCLK. Three clock rates are selectable by a programmable prescaler (see chapter clock generation figure 89) which is controlled by the MODE1.MCLK bit corresponding to the following table. ...
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IOM-2 Interface The SCOUT supports the IOM-2 interface in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates the start of an ...
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IOM-2 Frame Structure The frame structure on the IOM-2 data ports (DU,DD) in IOM-2 terminal mode is shown in figure 20 . Figure 20 IOM -2 Frame Structure in Terminal Mode The frame is composed of three channels • ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the SCOUT and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all time ...
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Figure 21 Architecture of the IOM Handler Data Sheet 38 PSB 21381/2 PSB 21383/4 Interfaces 2001-03-12 ...
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Controller Data Access (CDA) The IOM-2 handler provides with its four controller data access registers (CDA10, CDA11, CDA20, CDA21) a very flexible solution for the access to the 12 IOM-2 time slots by the microcontroller. The functional unit CDA ...
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TSa 1 0 Enable output input (EN_O0) (EN_I0) CDAx0 1 0 TSa a,b = 0...11 Figure 22 Data Access via CDAx0 and CDAx1 register pairs 2.2.2.1.1 Looping and Shifting Data Figure 23 gives examples ...
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Looping Data b) Shifting Data c) Switching Data . Figure 23 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting Data c) Switching Data Data Sheet TSa TSb CDAx0 CDAx0 .TSS: TSa ...
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Monitoring Data Figure 24 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots ...
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Synchronous Transfer While looping, shifting and switching (see figure 28 and 29) the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt (STOV). The microcontroller access to the CDAxy ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Figure 27 shows the timing of looping TSa TSa 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD ...
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Figure 28 shows the timing of shifting data from TSa to TSb on DU(DD). In figure 28a) shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,b = 0...9 and b a+2) In figure ...
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Serial Data Strobe Signal and strobed Data Clock For time slot oriented standard devices connected to the IOM-2 interface the SCOUT provides two independent data strobe signals SDS1 and SDS2. The SDS2 function is shared with the RSTO function ...
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Figure 29 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM-2 whereas in the second example during IC1 and IC2. The third example shows a strobe signal ...
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Strobed IOM-2 Bit Clock The strobed IOM bit clock is active during the programmed window (see chapter 7.3.8). Outside the programmed window a ’0’ is driven. Two examples are shown in figure 30. FSC DD, TS0 TS1 ...
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IOM-2 Monitor Channel The IOM-2 MONITOR channel (see figure 20) is utilized for information exchange between the SCOUT and other devices connected to the MONITOR channel. The MONITOR channel data can be controlled by the bits in the MONITOR ...
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The MONITOR channel can be used in following applications which are illustrated in figure 31: • master device the SCOUT can program and control other devices attached to the IOM-2 which do not need a microcontroller interface e.g. ...
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Handshake Procedure The MONITOR channel operates on an asynchronous basis. While data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the MONITOR Channel Receive (MR) and ...
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Transmission µC MIE=1 MOX=ADR MXC=1 MAC=1 MDA Int. MOX=DATA1 MDA Int. MOX=DATA2 MDA Int. MXC=0 MAC=0 Figure 32 MONITOR Channel Protocol (IOM-2) Data Sheet MON ADR ADR 0 ADR 0 ADR 0 DATA1 1 ...
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Before starting a transmission, the microcontroller should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the ...
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The MONITOR transfer protocol rules are summarized in the following section • A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. • A start ...
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MX/MR Treatment in Error Case: In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC respectively. An abort is indicated by an MAB interrupt or MER interrupt respectively. In the slave mode the ...
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IOM -2 Frame No (DU (DD) 0 Figure 35 Monitor Channel, normal End of Transmission 2.2.4.3 MONITOR Channel Programming as a Master Device As a master device the SCOUT can program and control other devices ...
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The first byte of the MONITOR message must contain in the higher nibble the MONITOR channel address code which is ’1010’ for the SCOUT. The lower nibble distinguishes between a programming command or an identification command. Identification Command In order ...
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MONITOR Time-Out Procedure To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must ...
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C/I Channel Handling The Command/Indication channel carries real-time status information between the SCOUT and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of ...
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If several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always ...
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D-Channel Access Control D-channel access control was defined to guarantee all connected HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible on the IOM-2 interface, if there are more than one HDLC controller connected, ...
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The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM- 2 interface (see figure 39). An access request to the TIC bus may either be generated by software ( P access to the C/I ...
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The availability of the line interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD last octet of channel 2 (figure 40). S stop S Figure 40 Structure of ...
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In the activated state the priority class may be changed whenever required by simply programming the desired activation request command (AR8 or AR10). Priority change is accepted without the double last-look criterion. The S-transceiver will not be transparent in transmit ...
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The following scheme illustrates a priority class 8/10 selection with NT initiated activation and with TE initiated activation 1. Priority Class 8/10 Selection with NT Initiated Activation TE IOM -2 C/I DC (1111b) C/I DI (1111b) C/I AR (1000b) C/I ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL = ’0’ and BCL = ’1’ ’ and the ...
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The clock pulses will be enabled again when the DU line is pulled low (e.g. bit SPU in the IOM_CR register) or when a non-zero level on the line interface is detected and TR_CONF0.LDD is set to ’0’. The clocks ...
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SPU = 1 FSC DU DD FSC DU 0 DCL Figure 43 Activation of the IOM-Interface Data Sheet CIC : CIXO = TIM Int IOM -CH1 IOM -CH2 IOM ...
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S/T Interface The layer-1 functions for the S/T interface of the SCOUT are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430 – conversion of the frame structure between IOM and S/T ...
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Figure 44 Wiring Configurations in User Premises Data Sheet ... 71 PSB 21381/2 PSB 21383/4 Interfaces Point-to-Point Configurations Short Passive Bus Extended Passive Bus 2001-03-12 ...
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Frame Structure Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data (B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see figure 45). In the direction TE ...
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Figure 45 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
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Multi-Framing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be the bits ...
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After multi-frame synchronization has been established, the Q data will be inserted at the upstream (TE NT) F bit position in each 5th S/T frame (see table 9). A When synchronization is not achieved or lost, each received F transmitted ...
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Phase Deviation The S/T transmitter is shifted by two S/T bits - 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. To compensate additional delay introduced into the receive and ...
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Control of Layer-1 The layer-1 activation/ deactivation can be controlled by an internal statemachine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the SCOUT-SX) ...
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Internal Layer-1 Statemachine In the following sections the layer-1 control by the SCOUT statemachine will be described. For the description of the IOM-2 C/I0 channel see also chapter 2.2.5. The layer-1 functions are controlled by commands issued via the ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 49 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a “+” ...
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Pending Act. TIM RSY TIM i4 F5 Unsynchronized Synchronized i3 i2 ix+ ix+ Activated i3 ...
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TMi TMi TMi TIM Test Mode Possible reset sources: C/I command RES software reset via SRES.RES_TR or reset from pin RST Figure 51 State Transition Diagram of the Unconditional Transitions 2.3.7.1.2 States F3 Pending ...
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F6 Synchronized The receiver has synchronized and detects info 2. Info 3 is transmitted to synchronize the NT. F7 Activated The receiver has synchronized and detects info 4. All user channels are now conveyed transparently to the IOM interface. To ...
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C/I Commands Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode 1 Test mode 2 Note: In the activated states (AI8, AI10 or AIL indication) ...
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C/I Indications Indication Deactivation Request Reset Test mode 1 Test mode 2 Resynchronization during level detect Power up Activation request Activation request loop ARL Far-end-code-violation CVR Activation indication loop Activation indication with priority class 8 Activation indication with priority ...
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Transmit Infos on S/T (Upstream) Name info 0 info 1 info 3 Test info 1 Test info 2 Data Sheet Abbr. Description i0 No signal on S/T i1 Continuous bit sequence of the form ’00111111’ Pulses are AMI-coded i3 ...
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Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown in figure 52. µC Interface IOM-2 Interface (C/I) SPU=0, CFS ...
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External Layer-1 Statemachine Instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. The internal layer-1 statemachine can be disabled by setting the L1SW bit in the TR_CONF0 register to ...
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Activation initiated by the Terminal (TE, SCOUT) INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is ...
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Activation initiated by the Network Termination NT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has ...
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Level Detection and Power Down If MODE1.CFS is set to ’0’, the clocks are also provided in power down state. If CFS is set to ’1’ only the analog level detector is active in power down state. All clocks, ...
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Test Functions The test and diagnostic functions for the S/T interface provided by the SCOUT are described in the following two chapters. 2.3.10.1 Transceiver Tests – The internal local loop (internal Loop A) is activated by a C/I0 ARL ...
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Test Signals Two kinds of test signals may be transmitted by the SCOUT: – The single pulses are of alternating polarity. One pulse is transmitted in each frame resulting in a frequency of the fundamental mode of 2 kHz). ...
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Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in ...
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Interface Circuitry For both, receive and transmit direction a 1:1 transformer is used to connect the SCOUT transceiver to the 4 wire S/T interface. The connections of the line transformers are shown in figure 58. Figure 58 Connection of ...
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Protection Circuitry for Transmitter SX1 GND SX2 Figure 59 External Circuitry for Transmitter Figure 59 illustrates the secondary protection circuit recommended for the transmitter. The external resistors (8 ... 10 pulse mask on the one hand and in order ...
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Figure 60 External Circuitry for Symmetrical Receivers Between each receive line and the transformer split into two resistors: one between transformer and protection diodes for current limiting during the 96 kHz test, and the second one between ...
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HDLC Controller The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD channel protocols. It can access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D) by setting the ...
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Non-Auto Mode (MDS2-0 = ’01x’) Characteristics: Full address recognition with one-byte (MDS = ’010’) or two-byte (MDS = ’011’) address comparison All frames with valid addresses are accepted and the bytes following the address are transferred to the P ...
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The transfer protocol between HDLC FIFO and microcontroller is block orientated with the microcontroller as master. The control of the data transfer between the CPU and the HDLC controller is handled via interrupts (HDLC controller (Host HDLC controller). There are ...
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The following description of the receive FIFIO operation is illustrated in figure 61 for a RFIFO block size (threshold and 32 bytes. The RFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which ...
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RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAH.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set complete frame is lost, ...
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Data Reception Procedure The general procedures for a data reception sequence are outlined in the flow diagram in figure 62 case of RME the last byte in RFIFO contains * the receive status information RSTA Figure ...
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Figure 63 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) is received. The FIFO threshold (block size) is set to 32 byte (EXMR.RFBS = ...
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Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see chapter 3.1) is shown in figure 64. Figure 64 Receive Data Flow Data Sheet FLAG ADDR CTRL ...
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The HDLC controller indicates to the host that a new data block can be read from the RFIFO by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received frame ...
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Data Transmission 3.3.1 Structure and Control of the Transmit FIFO 3.3.1.1 General Description The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds bytes, selectable by the XFBS bit in the EXMR register. There ...
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XFW (Transmit FIFO Write Enable), indicating that data can be written to the XFIFO. This status flag may be polled instead addition to XPR. The XFIFO requests service from the microcontroller by setting a bit in ...
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Possible Error Conditions during Transmission of Frames If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be raised. If the HDLC ...
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Data Transmission Procedure The general procedures for a data transmission sequence are outlined in the flow diagram in figure 65. Command XTF Figure 65 Data Transmission Procedure Data Sheet START Transmit N Pool Ready XPR ? Y Write Data ...
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The following description gives an example for the transmission byte frame with a selected block size of 32 byte (EXMR:XFBS=0): • The host writes 32 bytes to the XFIFO, issues an XTF command and waits for an ...
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Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in figure 67. For transparent frames, the whole frame including address and control field must be written to the XFIFO. The host configures whether the CRC is ...
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Extended Transparent Mode This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism. This allows user specific protocol ...
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HDLC Controller Interrupts The cause of an interrupt related to the HDLC controller is indicated by the HDLC bit in the ISTA register. This bit points at the different interrupt sources of the HDLC controller part in the ISTAH ...
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Test Functions The following test and diagnostic functions for the D-channel are available: – Digital loop via TLP (Test Loop, TMH register) command bit (figure 69): The TX path of layer 2 is internally connected with the RX path ...
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Codec The codec bridges the gap between the audio world of microphones, earphones, loudspeakers and the PCM digital world by providing a full PCM codec with all the necessary transmit and receive filters. Because the requirements for the codec ...
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The controlling and programming of the various operation modes, configurations and coefficients can be done via the microcontroller interface or the IOM-2 monitor channel and is described in the corresponding interface section. An overview on these programmable parameters can be ...
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Two differential inputs (MIP1/MIN1 and MIP2/MIN2) and one single-ended input (AXI) can be connected to the amplifier AMI via an analog input multiplexer (ATCR.AIMX). The programmable amplifier AMI (ATCR.MIC) provides a coarse gain adjustment range from 0...42dB in 6dB steps. ...
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Figure 72 AFE Attenuation Plan Data Sheet 119 PSB 21381/2 PSB 21383/4 Codec 2001-03-12 ...
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Signal Processor (DSP) Description The signal processor (DSP) has been conceived to perform all ITU-T and ETSI (NET33) recommended filtering in transmit and receive paths and is therefore fully compatible to the ITU-T G.712 and ETSI (NET33) specifications. The ...
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Figure 73 Processor Signal Flow Graph Data Sheet ...
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Transmit Signal Processing In the transmit direction a series of decimation filters reduces the sampling rate down to the 8-kHz PCM-rate. These filters attenuate the out-of-band noise by limiting the transmit signal to the voice band. The decimation stages ...
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The GR-gain adjustment stage is digitally programmable from – steps 0.25 dB (– dB and others are also possible). Respectively two bytes are coded in the CRAM to set GR to the desired value. After ...
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Programmable Coefficients for Transmit and Receive This section gives a short overview of important programmable coefficients. For more detailed information a coefficient software package is available (SCOUT MASTER SIPO 21383). Table 13 Description of the programmable Level Adjustment Parameters ...
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Tone Generation The ASP contains a universal tone generator which can be used for tone alerting, call progress tones, DTMF-signals or other audible feedback tones. All the tone generation configurations are programmable in the registers TGCR (Tone Generator Configuration ...
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Figure 75 Signal Flow Graph of the Tone Generation Unit Data Sheet 126 PSB 21381/2 PSB 21383/4 Codec 2001-03-12 ...
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Table 15 CRAM Parameters of the Signal and Sequence Generator Parameter # of CRAM Bytes Fn 2/2/2 Gn 1/1/1 Tn 2/2 GDn 1/1 either Note: 0-dB gain setting of G1 ...
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Control Generator Controlling of the generated tone follows the setting of the control bits ET (Enable Tone) and PT (Pulsed Tone) and the CRAM parameters TON and TOFF corresponding table 17 and table 18. Table 17 Control Generator ET ...
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Figure 76 Typical Control Generator Applications Data Sheet 129 PSB 21381/2 PSB 21383/4 Codec 2001-03-12 ...
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Tone Filter A programmable tone filter can be switched in the tone signal path by setting the ETF (Enable Tone Filter) bit. The tone filter contains a programmable equalizer and a saturation amplifier (see figure Chapter 75). A generated ...
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Figure 77 Filter Parameters of the Equalizer The two main purposes of the programmable saturation amplification are: • Level balancing of the filtered signal (avoidance of overload effects). • Amplification followed by a saturation (3.14 ...
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Tone Level Adjustment The generated tone signal can be amplified separate for transmit and receive direction with the gain parameters GTX, GTR and switched to the transmit/receive channels by setting TGSR.TRX (Tone Ringing Transmit) and TRR (Tone Ringing Receive). ...
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Table 21 DTMF-frequency (F3,FD) Programming ITU-T Q.23 SCOUT [Hz] Nominal [Hz] Low Group 697 697.1 770 770.3 852 852.2 941 941.4 High Group 1209 1209.5 1336 1336.9 1477 1477.7 1633 1632.8 Note: The deviations due to the inaccuracy of the ...
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Speakerphone Support The speakerphone option of the SCOUT-SX performs all functions required for echo suppression without any external components, just by software. All these operational functions realized by the signal processor are completely parameterized. This technique offers a high ...
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Signal-Processing & Analog Front End SX Signal-Processing SR & Analog Front End Figure 78 Speakerphone Signal Flow Graph of the SCOUT-SX 4.4.1 Attenuation Control Unit The Attenuation Control unit controls the attenuation stages GHX of the transmit and GHR of ...
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Description of the programmable parameters: Parameter # of CRAM Bytes TW 1 ATT 4.4.2 Speakerphone Test Function and Self Adaption For optimizing the speakerphone performance the SCOUT-SX provides following test functions: - The two register ...
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Figure 79 Speech Detector Signal Flow Graph 4.4.3.1 Background Noise Monitor The tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. ...
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A small fade constant (LP2N) enables fast settling down the LP2 to the average noise level after the end of speech recognition. However, a too small time constant for LP2N can cause rapid charging to such a high level that ...
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Description of the programmable speech detector parameters: Parameter # of CRAM Bytes LP1 1 OFF 1 PDS 1 PDN 1 LP2S 1 LP2N 1 LP2L 1 LIMX, LIMR 1 4.4.4 Speech Comparators (SC) Switching from one active mode to another ...
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Figure 80 Speech Comparator at the Acoustic Side At the SCAE-input, logarithmic amplifiers compress the signal range. Hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. Principally, the main task ...
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To control the acoustic feedback two parameters are necessary: GDAE-features the actual reserve on the measured GAE. Together with the Peak Decrement (PDAE) it simulates the echo behaviour at the acoustic side: After RX-speech has ended there is a short ...
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With speech, even if very strong resonances are present, the performance will not be worsened by the high GDSAE needed. Only when speech is detected, a high reserve prevents clipping. A time period ETAE [ms] after speech end, the parameters ...
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Figure 82 Speech Comparator at the Line Side The Gain of the Line Echo (GLE) directly corresponds to the echo return loss of the link. Generally specified to 27 dB. However, the worst case loss can be estimated ...
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Description of the programmable parameters: Parameter # of CRAM Bytes GLE 1 GDSLE 1 PDSLE 1 GDNLE 1 PDNLE 1 ETLE 1 4.4.4.3 Automatic Gain Control of the Transmit Direction (AGCX) Optionally an AGCX is inserted into the transmit path ...
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Figure 83 Block Diagram of the AGC in Transmit Direction For reasons of physiological acceptance the AGCX gain is automatically reduced in case of continuous background noise e.g. by ventilators. The reduction is programmed via the NOlSX-parameter. When the noise ...
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The initial gain (AGIX) is used immediately after enabling the AGCX to allow a fast settling time of the AGC. -50dBm0 -40dBm0 AGX=0...+18dB AGX Figure 84 Level Diagram For the AGC in Transmit Direction Data Sheet AGC INPUT LEVEL -30dBm0 ...
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Description of the programmable parameters: Parameter # of CRAM Bytes LGAX 1 COMX 1 AAX 1 AGX 1 AGIX 1 TMLX 1 TMHX 1 NOISX 1 4.4.5 Automatic Gain Control of the Receive Direction (AGCR) The Automatic Gain Control of ...
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Figure 85 Function of the Receive AGC Data Sheet 148 PSB 21381/2 PSB 21383/4 Codec 2001-03-12 ...
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AGR=0...+18dB AAR=0...-48dB AGR>0 AGR=0 Figure 86 Level Diagram For the AGC in Receive Direction If the speakerphone is in transmit mode, the AGCR is not working; instead the last gain setting is used and the regulation starts with ...
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Description of the programmable parameters: Parameter # of CRAM Bytes LGAR 1 COMR 1 AAR 1 AGIR 1 AGR 1 TMLR 1 TMHR 1 NOISR 1 4.4.6 Speakerphone Coefficient Set Table 22 shows a possible configuration for a speakerphone application ...
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Table 22 Basic Coefficient Set (cont’d) CMD Sequence Coefficient COP_C LIMX, LIMR COP_C OFFX COP_C OFFR COP_C LP2LX COP_C LP2LR COP_C LP1X COP_C LP1R COP_C reserved 00 COP_D PDSX COP_D PDNX COP_D LP2SX COP_D LP2NX COP_D PDSR COP_D PDNR COP_D ...
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Controlled Monitoring A so called “controlled monitoring” can be done when the bit GCR.CME is set. This mode can only be used together with the speakerphone mode (GCR.SP). With CME = ’1’ the attenuation stage GHR is fixed to ...
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Table 23 Voice Data Manipulation Register Bits DSSR DSS1X, DSS2X: Data Source Data Source Selection Register Selection CH1X, Data Source Selection CH2X DSSR: Data Source Selection Receive ENX1, ENX2: Enable Transmit CH1, CH2 DFR DF1R, DF2R: Data Format Data Format ...
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Test Functions The codec provides several test and diagnostic functions which can be grouped as follows: • All programmable configuration registers and coefficient RAM-locations are readable • Digital loop via PCM-register (DLP) • Digital loop via signal processor (DLS) ...
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Programming of the Codec During initialization of the codec a subset of configuration registers and coefficient RAM (CRAM) locations has to be programmed to set the configuration parameters according to the application and desired features. The codec can be ...
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Description of the Command Word (CMDW) Value after reset CMDW R/W 0 R/W 0: writing to configuration registers or to coefficient RAM 1: reading from configuration registers or from coefficient RAM CMDx Address to internal programmable ...
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Coding of Coefficient Operations (COP) Bit CMD Name COP_0 COP_1 COP_2 COP_3 COP_4 ...
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Direct Programming of the Codec The codec registers (60 H chapter 2.1 and 4.8.2.1). 4.8.2.1 CRAM Back-Up Procedure For the direct access to individual CRAM coefficients via microcontroller a back-up procedure is provided. This ensures that the codec DSP ...
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Access Data Flow Figure 87 CRAM Access Structure Figure 88 Signal Flow of the Back-up Procedure Data Sheet <CBADR_F> <CBADR_E> <CBADR_D> <CBADR_C> <CBADR_B> DCA = ’0’ <CBADR_A> <CBADR_9> <CBADR_8> <CBADR_7> <CBADR_6> <CBADR_5> <CBADR_4> <CBADR_3> <CBADR_2> <CBADR_1> <CBADR_0> DCA = ...
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Reference Tables for the Register and CRAM Locations Table 24 Configuration Registers Address CMDW Register WR/RD SOP_0 60 10 /90 GCR SOP_1 61 11 /91 PFCR SOP_2 62 12 /92 TGCR H H ...
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Table 24 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_3 63 13 /93 TGSR SOP_4 64 14 /94 ACR SOP_5 65 15 /95 ATCR SOP_6 66 16 /96 ARCR H H ...
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Table 24 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_8 68 18 /98 DSSR SOP_9 XCR H H -/99 XSR H if MAAR = ’0’ -/99 XSR H if MAAR = ’1’ SOP_A 6A ...
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Table 24 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_C 6C 1C /9C TFCR SOP_D 6D 1D /9D TMR1 SOP_E 6E 1E /9E TMR2 SOP_F - 1F /9F <DFR> ...
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Table 25 Coefficient RAM (CRAM) Address CMDW Mnemonic Description WR/RD COP_0: Tone generator parameter set / GD1 ...
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Table 25 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_4: Control generator A3 24 /A4 TON TOFF COP_5: Receive and transmit gain ...
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Table 25 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_8:Transmit correction filter part 1 to part 4 and receive correction filter part 9 to part / ...
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Table 25 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_B:Parameter set for transmit and receive speech comparator DF 2B /AB GDSAE PDSAE H DD GDNAE H DC PDNAE H DB GDSLE H DA PDSLE ...
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Table 25 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_E:Parameter set for transmit AGC F7 2E /AE LGAX COMX H F5 AAX H F4 AGX H F3 TMHX H F2 TMLX H F1 NOISX ...
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Clock Generation Figure 89 shows the clock system of the SCOUT. The oscillator is used to generate a 7.68 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous ...
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Jitter 5.1.1 Jitter on IOM-2 The DPLL only readjusts with each received F/L edge of the S interface. If the receiver has not yet synchronized the DPLL will adjust in one step. 5.1.2 Jitter on S The S transmit ...
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Reset The SCOUT can be reset completely by a hardware reset (pin RST). Additionally each functional block can be reset separately via register SRES. If enabled an exchange awake, subscriber awake or watchdog time-out can generate a reset on ...
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Reset Source Selection The internal reset sources C/I code change, EAW and Watchdog can be output at the low active reset pin RSTO/SDS2. The selection of these reset sources can be done with the RSS2,1 bits in the MODE1 ...
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External Reset Input At the active low RST input pin an external reset can be applied forcing the device into the reset state. This external reset signal is additionally fed to the RSTO/SDS2 output. The length of the reset ...
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Detailed Register Description The register mapping is shown in Figure 92. Figure 92 Register Mapping The register address range from 00-1F address range. The address range 20-2F handler. The register set ranging from 30-3F general configuration registers. The address ...
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HDLC Control Registers, CI Handler Name 7 6 RFIFO XFIFO ISTAH RME RPF MASKH RME RPF STAR XDOV XFW CMDR RMC RRES MODEH MDS2 MDS1 MDS0 EXMR XFBS RFBS TIMR CNT SAP1 SAP2 RBCL RBC7 RBCH 0 0 TEI1 TEI2 ...
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Transceiver, Interrupt, General Configuration Registers NAME 7 6 TR_ DIS_ 0 CONF0 TR TR_ 0 0 CONF1 TR_ DIS_ PDS CONF2 TX TR_STA RINF TR_CMD XINF SQRR MSYN MFEN SQXR 0 MFEN ISTATR 0 x MASKTR 0 1 ISTA 0 ...
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IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller Data Access Register (CH10) CDA11 Controller Data Access Register (CH11) CDA20 Controller Data Access Register (CH20) CDA21 Controller Data Access Register (CH21) ...
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Name 7 6 CDA1_ CDA2_ IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 CO_CR 0 0 TR_CR 0 0 HCI_CR DPS_ EN_ CI1 CI1 MON_CR DPS EN_ MON SDS1_CR ...
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Name 7 6 SDS_ 0 0 CONF MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Codec Configuration Registers Name 7 6 GCR SP AGCX AGCR MGCR CME PFCR GX GR TGCR ET DT TGSR ...
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MASK1R MASK2R TFCR 0 0 CCR 0 0 CSR 0 0 Name 7 6 NOP 1 1 Note: Address 80 -FF belong to the coefficient RAM (see chapter 4.8.3 and chapter H H 7.4.14) Data Sheet MASK1 MASK2 ALTF Reserved ...
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HDLC Control and C/I Registers 7.1.1 RFIFO - Receive FIFO 7 RFIFO A read access to any address within the range 00h-1Fh gives access to the “current” FIFO location selected by an internal pointer which is automatically incremented after ...
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ISTAH - Interrupt Status Register HDLC Value after reset ISTAH RME RPF RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMR.RFBS) or the last part ...
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MASKH - Mask Register HDLC Value after reset MASKH RME RPF Each interrupt source in the ISTAH register can be selectively masked by setting to ’1’ the corresponding bit in MASK. Masked interrupt status bits are ...
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CMDR - Command Register Value after reset CMDR RMC RRES RMC ... Receive Message Complete Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By setting this bit, the microcontroller confirms that it ...
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MODEH - Mode Register Value after reset MODEH MDS2 MDS1 MDS0 MDS2-0 ... Mode Select Determines the message transfer mode of the HDLC controller, as follows: MDS2-0 Mode Number of Address Bytes Reserved ...
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RAC ... Receiver Active The HDLC receiver is activated when this bit is set to ’1’ ’0’ the HDLC data is not evaluated in the receiver. DIM2-0 ... Digital Interface Modes These bits define the characteristics of ...
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RFBS … Receive FIFO Block Size RFBS RFBS Block Size Bit6 Bit5 Receive FIFO byte byte byte byte Note: A change of RFBS will take effect after a ...
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TIMR - Timer Register Value after reset TIMR CNT CNT ... CNT together with VALUE determine the time period T2 after which a TIN interrupt will be generated in the normal case CNT x ...
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RBCL - Receive Frame Byte Count Low Value after reset RBCL RBC7 RBC7-0 ... Receive Byte Count Eight least significant bits of the total number of bytes in a received message. 7.1.12 SAP2 - SAPI2 Register ...
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RBC11-8 ... Receive Byte Count Four most significant bits of the total number of bytes in a received message. Note: Normally RBCH and RBCL should be read by the microcontroller after an RME- interrupt in order to determine the number ...