DS2174Q Maxim Integrated Products, DS2174Q Datasheet - Page 10

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DS2174Q

Manufacturer Part Number
DS2174Q
Description
Telecom ICs Enhanced Bit Error R ate Tester T1-E1-J1
Manufacturer
Maxim Integrated Products
Type
Bit Error Rate Testerr
Datasheet

Specifications of DS2174Q

Operating Supply Voltage
3.3 V
Supply Current
50 mA
Mounting Style
SMD/SMT
Package / Case
PLCC-44

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2. PARALLEL CONTROL INTERFACE
Access to the registers is provided through a nonmultiplexed parallel port. The data bus is 8 bits wide; the
address bus is 4 bits wide. Control registers are accessed directly; memory for long repetitive patterns is
accessed indirectly. RCLK and TCLK are used to update counters and for all rising edge bits in the
register map (RSYNC, LC, TL, SBE). At slow clock rates, sufficient time must be allowed for these port
operations.
Table 2-A. Register Map
ADDRESS
0A
0C
0D
0B
0E
00
01
02
03
04
05
06
07
08
09
0F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
Control Register 1
Control Register 2
Control Register 3
Control Register 4
Status Register
Tap/Seed Register 0
Tap/Seed Register 1
Tap/Seed Register 2
Tap/Seed Register 3
TEST Register
Count Register 0
Count Register 1
Count Register 2
Count Register 3
Count Register 4
Count Register 5
REGISTER NAME
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