COM20020I3V-DZD-TR SMSC, COM20020I3V-DZD-TR Datasheet - Page 29

• Manufacturer Part Number: COM20020I3V-DZD-TR
• Description: Network Controller & Processor ICs 5Mbps ARCNET CTRL 2K x 8 ON-CHIP RAM
• Manufacturer: SMSC

Specifications of COM20020I3V-DZD-TR

• Mounting Style: SMD/SMT
• Package / Case: PLCC-28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10 Configuration Register
6.2.11 Sub-Address Register
SMSC COM20020I Rev D
Status Register
The COM20020ID Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are
software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the
Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20020ID, the
COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these
bits exist in and are controlled by the Configuration Register. The Status Register contents are defined as
in Table 6.3, but are defined differently during the Command Chaining operation. Please refer to the
Command Chaining section for the definition of the Status Register during Command Chaining operation.
The Status Register defaults to the value 1XX1 0001 upon either hardware or software reset.
Diagnostic Status Register
The Diagnostic Status Register contains seven read-only bits which help the user troubleshoot the network
or node operation. Various combinations of these bits and the TXEN bit of the Configuration Register
represent different situations. All of these bits, except the Excessive NAcK bit and the New Next ID bit, are
reset to logic "0" upon reading the Diagnostic Status Register or upon software or hardware reset. The
EXCNAK bit is reset by the "POR Clear Flags" command or upon software or hardware reset. The
Diagnostic Status Register defaults to the value 0000 000X upon either hardware or software reset.
Command Register
Execution of commands are initiated by performing microcontroller writes to this register.
combinations of written data other than those listed in Table 6.4 are not permitted and may result in
incorrect chip and/or network operation.
Address Pointer Registers
These read/write registers are each 8-bits wide and are used for addressing the internal RAM. New pointer
addresses should be written by first writing to the High Register and then writing to the Low Register
because writing to the Low Register loads the address. The contents of the Address Pointer High and Low
Registers are undefined upon hardware reset. Writing to Address Pointer low loads the address.
The Configuration Register is a read/write register which is used to configure the different modes of the
COM20020ID. The Configuration Register defaults to the value 0001 1000 upon hardware reset only.
SUBAD0 and SUBAD1 point to the selection in Register 7.
The sub-address register is new to the COM20020ID, previously a reserved register. Bits 2, 1 and 0 are
used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the
Configuration register on the COM20020B. They are exactly same as those in the Sub-Address register. If
the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in the
Sub-Address register are also changed. SUBAD2 is a new sub-address bit. It Is used to access the 1 new
Set Up register, SETUP2. This register is selected by setting SUBAD2=1. The SUBAD2 bit is cleared
automatically by writing the Configuration register.
DATASHEET
Page 29
Revision 12-05-06
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