LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 27
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LAN9220-ABZJ
Manufacturer Part Number
LAN9220-ABZJ
Description
Ethernet ICs 16Bit Single Chip Ethernet Controller
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN9220-ABZJ.pdf
(151 pages)
Specifications of LAN9220-ABZJ
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
85 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9220-ABZJ
Manufacturer:
RENESAS
Quantity:
101
Part Number:
LAN9220-ABZJ
Manufacturer:
SMSC
Quantity:
20 000
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
Reserved
FIELD
FIELD
30:0
2:1
31
3
0
Filter 3 Offset
The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether
or not this is a wake-up frame.
The Filter i command register controls Filter i operation.
The Filter i Offset register defines the offset in the frame’s destination address field from which the
frames are examined by Filter i.
DESCRIPTION
Must be zero (0)
Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset
+ j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored.
DESCRIPTION
Address Type: Defines the destination address type of the pattern. When bit is set, the pattern
applies
only to multicast frames. When bit is cleared, the pattern applies only to unicast frames.
RESERVED
Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled.
Command
Filter 3
Filter 1 CRC-16
Filter 3 CRC-16
Table 3.2 Wake-Up Frame Filter Register Structure
Reserved
Table 3.3 Filter i Byte Mask Bit Definitions
Table 3.4 Filter i Command Bit Definitions
Filter 2 Offset
FILTER I BYTE MASK DESCRIPTION
Command
Table
FILTER i COMMANDS
Table 3.5
Filter 2
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
DATASHEET
3.3, describes the byte mask’s bit fields.
27
describes the Filter i Offset bit fields.
Reserved
Filter 1Offset
Table 3.4
Command
Filter 1
Filter 0 CRC-16
Filter 2 CRC-16
shows the Filter I command register.
Reserved
Filter 0 Offset
Revision 2.7 (03-15-10)
Command
Filter 0