LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 21

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BYTE
BYTE
HIGH
LOW
I/O SPACE
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
OFFSET
ALGNERR - Frame had alignment error. When MII SEL=1 alignment error is set when BADCRC=1 and an
odd number of nibbles was received between SFD and RX_DV going inactive. When MII SEL=0 alignment
error is set when BADCRC=1 and the number of bits received between SFD and the CRS going inactive is
not an octet multiple.
BRODCAST - Receive frame was broadcast.
BADCRC - Frame had CRC error, or RX_ER was asserted during reception.
ODDFRM - This bit when set indicates that the received frame had an odd number of bytes.
TOOLNG - Frame length was longer than 802.3 maximum size (1518 bytes on the cable).
TOOSHORT - Frame length was shorter than 802.3 minimum size (64 bytes on the cable).
HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by receive
routines to speed up the group address search. The hash value consists of the six most significant bits of
the CRC calculated on the Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the
hash value select a byte of the multicast table, while bits 2,1,0 determine the bit within the byte selected.
Examples of the address mapping:
MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set,
and the address was a multicast, the packet will pass address filtering regardless of other filtering criteria.
The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the I/O
space requirements to 16 locations, the registers are assigned to different banks. The last word of the I/O
area is shared by all banks and can be used to change the bank in use. Registers are described using the
following convention:
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided
the bank select has the appropriate value.
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit
registers, in that case the offset of each one is independently specified.
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
bit 15
bit 7
X
X
ED 00 00 00 00 00
0D 00 00 00 00 00
01 00 00 00 00 00
2F 00 00 00 00 00
ADDRESS
bit 14
bit 6
X
X
NAME
bit 13
bit 5
X
X
HASH VALUE 5-0
DATASHEET
000 000
010 000
100 111
111 111
Page 21
bit 12
bit 4
X
X
TYPE
bit 11
bit 3
X
X
MULTICAST TABLE BIT
bit 10
bit 2
MT-0 bit 0
MT-2 bit 0
MT-4 bit 7
MT-7 bit 7
X
X
SYMBOL
Revision 1.0 (09-22-08)
bit 9
bit 1
X
X
bit 8
bit 0
X
X