CS8900A-IQZR Cirrus Logic Inc, CS8900A-IQZR Datasheet - Page 78

• Manufacturer Part Number: CS8900A-IQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.0 OPERATION
5.1 Managing Interrupts and Servicing the
Interrupt Status Queue
The Interrupt Status Queue (ISQ) is used by
the CS8900A to communicate Event reports to
the host processor. Whenever an event occurs
that
CS8900A sets the appropriate bit(s) in one of
five registers, maps the contents of that regis-
ter to the ISQ, and drives the selected interrupt
request pin high (if an earlier interrupt is wait-
ing in the queue, the interrupt request pin will
already be high). When the host services the
interrupt, it must first read the ISQ to learn the
nature of the interrupt. It can then process the
interrupt (the first read to the ISQ causes the
interrupt request pin to go low.)
Three of the registers mapped to the ISQ are
event registers: RxEvent (Register 4), TxEvent
(Register 8), and BufEvent (Register C). The
other two registers are counter-overflow re-
ports: RxMISS (Register 10) and TxCOL (Reg-
ister 12). There may be more than one
RxEvent report and/or more than one TxEvent
report in the ISQ at a time. However, there
may be only one BufEvent report, one RxMISS
report and one TxCOL report in the ISQ at a
time.
Event reports stored in the ISQ are read out in
the order of priority, with RxEvent first, fol-
lowed by TxEvent, BufEvent, RxMiss, and
then TxCOL. The host only needs to read from
one location to get the interrupt currently at the
front of the queue. In Memory Mode, the ISQ
is located at PacketPage base + 0120h. In I/O
Mode, it is located at I/O base + 0008h. Each
time the host reads the ISQ, the bits in the cor-
responding register are cleared and the next
report in the queue moves to the front.
When the host starts reading the ISQ, it must
read and process all Event reports in the
78
triggers
an
enabled
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interrupt,
the
queue. A read-out of a null word (0000h) indi-
cates that all interrupts have been read.
The ISQ is read as a 16-bit word. The lower six
bits (0 through 5) contain the register number
(4, 8, C, 10, or 12). The upper ten bits (6
through F) contain the register contents. The
host must always read the entire 16-bit word.
The active interrupt pin (INTRQx) is selected
via the Interrupt Number register (PacketPage
base + 22h). As an additional option, all of the
interrupt pins can be 3-Stated using the same
register. see Section 4.3 on page 44.
An event triggers an interrupt only when the
EnableIRQ bit of the Bus Control register (bit F
of register 17) is set. After the CS8900A has
generated an interrupt, the first read of the ISQ
makes the INTRQ output pin go low (inactive).
INTRQ remains low until the null word (0000h)
is read from the ISQ, or for 1.6us, whichever is
longer.
5.2 Basic Receive Operation
5.2.0.1 Overview
Once an incoming packet has passed through
the analog front end and Manchester decoder,
it goes through the following three-step re-
ceive process:
1) Pre-Processing
2) Temporary Buffering
3) Transfer to Host
Figure 20 shows the steps in frame reception.
As shown in the figure, all receive frames go
through the same pre-processing and tempo-
rary buffering phases, regardless of transfer
method
Once a frame has been pre-processed and
buffered, it can be accessed by the host in ei-
ther Memory or I/O space. In addition, the
CS8900A can transfer receive frames to host
Crystal LAN™ Ethernet Controller
CS8900A
DS271F5