CS8900A-IQZR Cirrus Logic Inc, CS8900A-IQZR Datasheet - Page 76

• Manufacturer Part Number: CS8900A-IQZR
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 5V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-IQZR

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

eration. The Transmit Command tells the
CS8900A that the host has a frame to be
transmitted, as well as how that frame should
be transmitted. This port is mapped into Pack-
etPage base + 0144h. See Register 9 in
Section 4.4 on page 49 for more information.
4.10.3 TxLength Port
The length of the frame to be transmitted is
written here immediately after the Transmit
Command is written. This port is mapped into
PacketPage base + 0146h.
4.10.4 Interrupt Status Queue Port
This port contains the current value of the In-
terrupt Status Queue (ISQ). The ISQ is located
at PacketPage base + 0120h. For a more de-
tailed description of the ISQ, see Section 5.1
on page 78.
4.10.5 PacketPage Pointer Port
The PacketPage Pointer Port is written when-
ever the host wishes to access any of the
CS8900A's internal registers. The first 12 bits
(bits 0 through B) provide the internal address
of the target register to be accessed during the
current operation. The next three bits (C, D,
and E) are read-only and will always read as
011b. Any convenient value may be written to
these bits when writing to the PacketPage
Pointer Port. The last bit (Bit F) indicates
whether or not the PacketPage Pointer should
be auto-incremented to the next word location.
Figure 18 shows the structure of the Packet-
Page Pointer.
4.10.6 PacketPage Data Ports 0 and 1
The PacketPage Data Ports are used to trans-
fer data to and from any of the CS8900A's in-
ternal registers. Port 0 is used for 16-bit
operations and Port 0 and 1 are used for 32-bit
operations (lower-order word in Port 0).
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CIRRUS LOGIC PRODUCT DATASHEET
4.10.7 I/O Mode Operation
For an I/O Read or Write operation, the AEN
pin must be low, and the 16-bit I/O address on
the ISA System Address bus (SA0 - SA15)
must match the address space of the
CS8900A. For a Read, the IOR pin must be
low, and for a Write, the IOW pin must be low.
Note: The ISA Latchable Address Bus (LA17 -
LA23) is not needed for applications that use
only I/O Mode and Receive DMA operation.
4.10.8 Basic I/O Mode Transmit
I/O Mode transmit operations occur in the fol-
lowing order (using interrupts):
1) The host bids for storage of the frame by
2) The host reads the BusST register (Regis-
F E
writing the Transmit Command to the TxC-
MD Port (I/O base + 0004h) and the trans-
mit frame length to the TxLength Port (I/O
base + 0006h).
ter 18) to see if the Rdy4TxNOW bit (Bit 8)
is set. To read the BusST register, the host
must first set the PacketPage Pointer at the
correct location by writing 0138h to the
PacketPage Pointer Port (I/O base +
000Ah). It can then read the BusST regis-
ter from the PacketPage Data Port (I/O
I/O base + 000Bh
D C
Figure 18. PacketPage Pointer
Bit F: 0 = Pointer remains fixed
Crystal LAN™ Ethernet Controller
B A
1 = Auto-Increments to next word location
9 8
PacketPage Register Address
7 6
I/O base + 000Ah
5 4
3 2
CS8900A
1 0
DS271F5