ISPGDX160VA-5B208 Lattice, ISPGDX160VA-5B208 Datasheet - Page 19
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ISPGDX160VA-5B208
Manufacturer Part Number
ISPGDX160VA-5B208
Description
Analog & Digital Crosspoint ICs 3.3V 160 I/O
Manufacturer
Lattice
Datasheet
1.ISPGDX160VA-5BN208.pdf
(36 pages)
Specifications of ISPGDX160VA-5B208
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
2.3 V, 3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V, 3.3 V
Supply Type
Dual
Configuration
Programmable
Package / Case
TSSOP-24
Input Level
TTL
Output Level
TTL
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPGDX160VA-5B208
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
ISPGDX160VA-5B208I
Manufacturer:
LATTICE
Quantity:
1 510
Company:
Part Number:
ISPGDX160VA-5B208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
1. All timings measured with one output switching, fast output slew rate setting, except
PARAMETER
External Timing Parameters
t
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd
sel
max (Tog.)
max (Ext.)
su1
su2
su3
su4
suce1
suce2
suce3
h1
h2
h3
h4
hce1
hce2
hce3
gco1
gco2
co1
co2
en
dis
toeen
toedis
wh
wl
rst
rw
sl
sk
COND.
TEST
C
C
D
A
A
A
A
A
A
B
B
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
#
Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX)
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
Clock Frequency, Max. Toggle
Clock Frequency with External Feedback
Input Latch or Register Setup Time Before Y
Input Latch or Register Setup Time Before I/O Clock
Output Latch or Register Setup Time Before Y
Output Latch or Register Setup Time Before I/O Clock
Global Clock Enable Setup Time Before Y
Global Clock Enable Setup Time Before I/O Clock
I/O Clock Enable Setup Time Before Y
Input Latch or Register Hold Time (Y
Input Latch or Register Hold Time (I/O Clock)
Output Latch or Register Hold Time (Y
Output Latch or Register Hold Time (I/O Clock)
Global Clock Enable Hold Time (Y
Global Clock Enable Hold Time (I/O Clock)
I/O Clock Enable Hold Time (Y
Output Latch or Register Clock (from Y
Input Latch or Register Clock (from Y
Output Latch or Register Clock (from I/O pin) to Output Delay
Input Latch or Register Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset Pulse Width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 Across Chip)
Over Recommended Operating Conditions
DESCRIPTION
x
)
18
x
)
x
x
)
) to Output Delay
x
x
x
)
) to Output Delay
Specifications ispGDX160V
(
x
tsu3+tgco1
x
x
1
)
t
sl
.
MIN. MAX.
10.0
143
110
4.0
3.0
4.0
3.0
2.5
1.5
4.5
0.0
1.5
0.0
1.5
0.0
1.5
0.0
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
-5
14.0
5.0
6.5
5.0
8.5
6.0
9.5
6.0
6.0
9.0
9.0
8.0
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MIN. MAX.
80.0
14.0
100
5.5
4.5
5.5
4.5
3.5
2.5
6.5
0.0
2.5
0.0
2.5
0.0
2.5
0.0
5.0
5.0
–
–
–
–
–
–
–
–
–
–
–
–
–
-7
11.0
13.0
12.0
12.0
18.0
12.0
7.0
9.0
7.0
9.0
8.5
8.5
0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns