ISPGDX160VA-5B208 Lattice, ISPGDX160VA-5B208 Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
ISPGDX160VA-5B208
Manufacturer Part Number
ISPGDX160VA-5B208
Description
Analog & Digital Crosspoint ICs 3.3V 160 I/O
Manufacturer
Lattice
Datasheet
1.ISPGDX160VA-5BN208.pdf
(36 pages)
Specifications of ISPGDX160VA-5B208
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
2.3 V, 3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V, 3.3 V
Supply Type
Dual
Configuration
Programmable
Package / Case
TSSOP-24
Input Level
TTL
Output Level
TTL
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISPGDX160VA-5B208
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
ISPGDX160VA-5B208I
Manufacturer:
LATTICE
Quantity:
1 510
Company:
Part Number:
ISPGDX160VA-5B208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Inputs
t
GRP
t
MUX
t
t
t
t
t
t
Register
t
t
t
t
t
t
t
Data Path
t
t
t
t
t
t
t
Outputs
t
t
t
t
t
t
Clocks
t
t
t
t
t
t
Global Reset
io
grp
muxd
muxexp
muxs
muxsio
muxsg
muxselexp
iolat
iosu
ioh
ioco
ior
cesu
ceh
fdbk
iobp
ioob
muxcg
muxcio
iodg
iodio
ob
obs
oeen
oedis
goe
toe
ioclk
gclk
gclkeng
gclkenio
ioclkeng
gr
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
52
53
54
55
56
57
58
59
60
61
62
63
64
65
50
51
#
Input Buffer Delay
GRP Delay
I/O Cell MUX A/B/C/D Data Delay
I/O Cell MUX A/B/C/D Expander Delay
I/O Cell Data Select
I/O Cell Data Select (I/O Clock)
I/O Cell Data Select (Yx Clock)
I/O Cell MUX Data Select Expander Delay
I/O Latch Delay
I/O Register Setup Time Before Clock
I/O Register Hold Time After Clock
I/O Register Clock to Output Delay
I/O Reset to Output Delay
I/O Clock Enable Setup Time Before Clock
I/O Clock Enable Hold Time After Clock
I/O Register Feedback Delay
I/O Register Bypass Delay
I/O Register Output Buffer Delay
I/O Register A/B/C/D Data Input MUX Delay (Yx Clock)
I/O Register A/B/C/D Data Input MUX Delay (I/O Clock)
I/O Register I/O MUX Delay (Yx Clock)
I/O Register I/O MUX Delay (I/O Clock)
Output Buffer Delay
Output Buffer Delay (Slow Slew Option)
I/O Cell OE to Output Enable
I/O Cell OE to Output Disable
GRP Output Enable and Disable Delay
Test OE Enable and Disable Delay
I/O Clock Delay
Global Clock Delay
Global Clock Enable (Yx Clock)
Global Clock Enable (I/O Clock)
I/O Clock Enable (Yx Clock)
Global Reset to I/O Register Latch
Over Recommended Operating Conditions
1
DESCRIPTION
14
1
Specifications ispGDX160VA
MIN. MAX. MIN. MAX. UNITS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
0.4
1.1
1.0
1.5
1.0
1.5
1.5
1.5
1.0
0.8
1.7
1.2
1.0
2.3
0.2
0.6
0.0
0.0
1.5
1.5
3.5
3.5
1.0
4.5
3.5
3.5
0.0
2.5
0.3
1.3
1.5
1.0
0.5
6.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
11.0
0.9
1.1
1.5
2.0
1.5
3.0
2.0
2.0
1.0
2.0
1.5
0.5
1.5
2.0
0.5
0.9
0.0
0.0
2.0
3.0
4.0
5.0
1.5
6.5
4.0
4.0
0.0
2.0
2.0
2.0
2.5
3.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns