LX256V-5F484C Lattice, LX256V-5F484C Datasheet - Page 17

• Manufacturer Part Number: LX256V-5F484C
• Description: Analog & Digital Crosspoint ICs 3.3V 256 I/O
• Manufacturer: Lattice

Specifications of LX256V-5F484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Operating Modes
All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and
FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB
connects to the output register. Inputs are connected to the GRP via the MRB.
Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERDES connections is pro-
vided in their respective sections.
Figure 11. Four Operating Modes of ispGDX2 Devices
FIFO Operations
Each GDX Block is associated with a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two
address counters and two comparators, is used to implement a FIFO as a “circular queue”. The FIFO has separate
clocks, the Read Clock (RCLK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three addi-
tional control signals Write Enable, Read Enable and FIFO Reset. Three flags show the status of the FIFO: Empty,
Full and Start Read. Each FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the con-
nections to the FIFO.
FIFO Mode GRP
Flow-through
SERDES
SERDES
*FIFO held in RESET for SERDES-only mode.
(FIFO in
Basic
Mode
Mode
Mode
FIFO
Mode)
and
GRP
GRP
GRP
Block
Block
Block
Block
GDX
GDX
GDX
GDX
14
FIFO*
FIFO
FIFO
FIFO
SERDES
SERDES
SERDES
SERDES
ispGDX2 Family Data Sheet
sysIO
sysIO
sysIO
sysIO
Bank
Bank
Bank
Bank