LX128EV-5F208I Lattice, LX128EV-5F208I Datasheet - Page 32
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LX128EV-5F208I
Manufacturer Part Number
LX128EV-5F208I
Description
Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 3.3V, 5ns, IND
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX128EV-5F208I
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
3.3 V
Supply Type
Triple
Configuration
128 x 128
Package / Case
FPBGA-208
Data Rate
21 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LX128EV-5F208I
Manufacturer:
LATTICE
Quantity:
482
Company:
Part Number:
LX128EV-5F208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Timing Model
The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in
Figure 18 shows the specific delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report file, the delay path of the function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model for a particular design.
Note that the internal timing parameters are given for reference only, and are not tested. The external timing param-
eters are tested and guaranteed for every device.
Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)
Italicized parameters are optional.
Model Version 1.6.7
GCLKEN
GCLK/
GSEL
TOE/
GOE
GSR
IN
t
CLKEN_IN
t
t
t
t
t
CLK_IN
TOE_IN
GOE_IN
SEL_IN
t
t
SR_IN
t
t
t
t
IOI
IOI
IOI
IOI
IOI
IN
from GRP
from GRP
from GRP
from Adjacent Cells
TOE path
GOE path
(RECCLK, SYDT)
(PLL Output)
from sysHSI
from FIFO
from PLL
(DOUT)
(Input)
to sysHSI/FIFO
(Global Reset)
t
PLL_SEC_DELAY
t
PLL_DELAY
t
GCLK
t
from GRP
t
t
PTSEL
PTSR
PTOE
(SIN, Control, DIN, I/O Reset, SSCLKIN)
t
FIFODATAOUT
t
t
to sysHSI/FIFO
HSIOUT
t
t
PLLOUT
INDIO
IPAC
from GRP
t
t
MUXSEL
MUXPD
to sysHSI
(REFCLK)
(WCLK)
to FIFO
from Adjacent
Cells (Output)
t
PTCLKEN
t
PTCLK
t
OPAC
29
to FIFO
(WE)
CE
S/R
CE
S/R
S/R
CE
D
D
D
Output Reg.
t
t
Input Reg.
OPBYPASS
t
OE Reg.
OEBYPASS
IPBYPASS
Q
Q
Q
from sysHSI/FIFO
(SSCLKOUT)
from sysHSI
from sysHSI
(SOUT)
(Flags)
ispGDX2 Family Data Sheet
t
t
t
HSIFIFOFLAG
HSISSCLKOUT
HSISOUT
t
ROUTEGRP
Output
Delays
t
t
t
t
BUF
EN
DIS
IOO
to Adjacent Cells
to Adjacent Cells
OUT
to sysHSI
(Output)
to FIFO
to FIFO
(RCLK)
to GRP
(TXD)
(Input)
(REN)