DS2172TN/T&R Maxim Integrated Products, DS2172TN/T&R Datasheet - Page 12

• Manufacturer Part Number: DS2172TN/T&R
• Description: Communication ICs - Various
• Manufacturer: Maxim Integrated Products
• Type: Bit Error Rate Testerr

Specifications of DS2172TN/T&R

• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Supply Type: Analog
• Package / Case: TQFP-32
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current: 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.0 PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
PATTERN RECEIVE REGISTERS
11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS2172. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
(MSB)
PR31
PR23
PR15
PR7
PR30
PR22
PR14
PR6
PR29
PR21
PR13
PR5
PR28
PR20
PR12
PR4
PR27
PR19
PR11
PR3
PR26
PR18
PR10
PR2
12 of 22
PR25
PR17
PR9
PR1
(LSB)
PR24
PR16
PR8
PR0
INT
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
pin. Each of the alarms
DS2172