LX256V-5FN484C Lattice, LX256V-5FN484C Datasheet - Page 14

• Manufacturer Part Number: LX256V-5FN484C
• Description: Analog & Digital Crosspoint ICs 256 I/O Switch Matrix, 3.3V, SERDES, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX256V-5FN484C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 256 x 256
• Package / Case: FPBGA-484
• Data Rate: 38 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 7. I/O Pin Connection to the sysCLOCK PLL
GCLK_IN
1. Some pins are shared. See Logic Signal Connections Table for details.
GCLK_IN
Input Clock
(M) Divider
÷ 1 to 32
PLL_RST
--------------------
Programmable
Programmable
Divider (N)
Feedback
x 1 to 32
+ Delay
- Delay
PLL_FBK
PLL (n)
Post-scalar
(V) Divider
(K) Divider
1, 2, 4, 8,
2, 4, 8,
16, 32
16, 32
Clock
÷
÷
To Adjacent_PLL
From Adjacent_PLL
Clock Net
PLL_LOCK
1
CLK_OUT
11
GRP
Resetb (0)
(from selected blocks)
Control Array
ispGDX2 Family Data Sheet
GDX Block
Output
Latch
Input
Reg/
Latch
Reg/
Delay