ISPGDX240VA-7BN388 Lattice, ISPGDX240VA-7BN388 Datasheet - Page 16

• Manufacturer Part Number: ISPGDX240VA-7BN388
• Description: Analog & Digital Crosspoint ICs PROGRAMMABLE GEN DIG CROSSPOINT
• Manufacturer: Lattice

Specifications of ISPGDX240VA-7BN388

• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Single
• Configuration: 240 x 240
• Package / Case: PLCC-28
• Input Level: TTL
• Output Level: TTL
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ispGDXVA devices provide IEEE1149.1a test capa-
bility and ISP programming through a standard Boundary
Scan Test Access Port (TAP) interface.
The boundary scan circuitry on the ispGDXVA Family
operates independently of the programmed pattern. This
allows customers using boundary scan test to have full
test capability with only a single BSDL file.
Figure 7. Boundary Scan I/O Register Cell
Table 2. I/O Shift Register Order
Table 3. ispGDX240VA Device ID Codes
Boundary Scan
ispGDX240VA
ispGDX240VA
DEVICE
DEVICE
SCANIN
(from
previous
cell)
TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B30 .. B59, I/O C0 .. C59, I/O D0 .. D29, I/O B29 .. B0,
I/O A59.. A0, I/O D59 .. D30, TDO
0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011
Shift DR
32-BIT BOUNDARY SCAN ID CODE
M
U
X
M
U
X
M
U
X
Clock DR
D
D
D
Q
Q
Q
I/O SHIFT REGISTER ORDER
Update DR
ID Code/GDX240VA
16
SCANOUT (to next cell)
D
The ispGDXVA devices are identified by the 32-bit JTAG
IDCODE register. The device ID assignments are listed
in Table 3.
The ispJTAG programming is accomplished by execut-
ing Lattice private instructions under the Boundary Scan
State Machine.
Contact Lattice Applications to obtain more detailed
programming information.
D
Specifications ispGDX240VA
Q
Q
Function
Function
Normal
Normal
OE
OE
M
U
X
M
U
X
EXTEST
TOE
I/O Pin
I/O Shift Reg Order/ispGDX240