ETHER-FAST-XP-N3 Lattice, ETHER-FAST-XP-N3 Datasheet - Page 8

• Manufacturer Part Number: ETHER-FAST-XP-N3
• Description: Ethernet ICs Ethernet MAC 10/100 Mbps
• Manufacturer: Lattice

Specifications of ETHER-FAST-XP-N3

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10/100 and 1Gig Ethernet
Lattice Semiconductor
Media Access Controller User’s Guide
Host Interface
The Host Interface module is a fully synchronous module that runs off the host clock. A number of registers are ini-
tialized via the Host interface to ensure that the Tri-Speed MAC functions as intended. The write operation to an
internal register is initiated when the hcs_n and hwrite_n signals are asserted and hread_n signal is de-
asserted. The address of the targeted register is placed on the haddr bus, while the valid data is placed on the
hdatain bus. The contents of the address and data busses should remain unchanged until the Tri-Speed MAC core
asserts the hready_n
signal. The signals cs_n, hwrite_n and hread_n must remain unchanged until
hready_n is asserted.
A register read is initiated by asserting the hcs_n and hread_n signals, while keeping the hwrite_n signal de-
asserted. The address of the targeted register is placed on the haddr bus. The Tri-Speed MAC places the content
of the targeted register on the hdataout bus and qualifies it with the assertion of hready_n signal. The haddr
bus should not change until the hready_n signal is asserted.
Figure 9 shows the timing diagram associated with the host interface write and read operations.
Receive MAC (Rx MAC)
The main function of the Rx MAC is to accept the formatted data from the G/MII interface and pass it to the host
through an external FIFO. In this process, the Rx MAC performs the following functions:
• Detect the Start of Frame
• Compare the MAC address
• Re-calculate CRC
• Process the Control Frame and pass it to the flow control module.
The Rx MAC operation is determined by programming the MODE and TX_RX_CTL registers.
Programming the MODE and TX_RX_CTL registers can control the Receive MAC operation. The various events
that occur during the reception of a frame are logged into the rx_stat_vector signal and the TX_RX_STS regis-
ter. At the end of reception, the rx_stat_en signal is asserted to qualify the rx_stat_vector signal. The Tri-
Speed MAC core can report a wealth of information such as
• FIFO overflow
• CRC error
• Receive error
• Short frame reception
• Long frame reception
• IPG violation
By default, the entire frame, except the preamble and SFD bytes, is sent to the FIFO via the Rx MAC Application
Interface signals. If the user does not want to receive the FCS, the core can be programmed to strip the FCS field
as well as any PAD bytes in the frame and send the rest to the FIFO.
The Rx MAC section operates on the rx_clk sourced from the PHY in the 10/100 mode. All the signals on the
Receive MAC FIFO interface are synchronous to this clock. The Rx MAC operation is synchronized to an internal
clock when the Tri-Speed MAC is in the Gigabit mode. This internal clock is a divided-by-two version of the rx_clk
from the external PHY device. In this case, the divided clock is output to the FIFO interface as rx_appclk. The
output signals from the Rx MAC interface are synchronous to this clock.
The Rx MAC is disabled while reset_n is low and should only be enabled after the associated registers are prop-
erly initialized.
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