DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 8

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

DS21455/DS21458 Quad T1/E1/J1 Transceivers
LIST OF TABLES
Table 5-1. DS21455 PIN DESCRIPTION .................................................................................................................. 29
Table 5-2. DS21458 PIN DESCRIPTION .................................................................................................................. 34
Table 6-1. REGISTER MAP SORTED BY ADDRESS .............................................................................................. 41
Table 10-1. T1 ALARM CRITERIA ............................................................................................................................ 63
Table 11-1. E1 SYNC/RESYNC CRITERIA .............................................................................................................. 65
Table 11-2 AUTO E-BIT CONDITIONS..................................................................................................................... 68
Table 11-3. E1 ALARM CRITERIA ............................................................................................................................ 70
Table 14-1. LIUC CONTROL..................................................................................................................................... 82
Table 15-1. T1 LINE CODE VIOLATION COUNTING OPTIONS ............................................................................. 86
Table 15-2. E1 LINE CODE VIOLATION COUNTING OPTIONS............................................................................. 86
Table 15-3. T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS ............................................................. 88
Table 15-4. T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS.............................................................. 89
Table 17-1. TIME SLOT NUMBERING SCHEMES................................................................................................. 101
Table 18-1. IDLE CODE ARRAY ADDRESS MAPPING......................................................................................... 108
Table 20-1. ELASTIC STORE DELAY AFTER INITIALIZATION............................................................................ 120
Table 24-1. HDLC CONTROLLER REGISTERS .................................................................................................... 142
Table 25-1. TPD CONTROL.................................................................................................................................... 164
Table 25-2. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0)............................. 165
Table 25-3. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1)............................ 165
Table 25-4. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0) ............................. 165
Table 25-5. T1 MODE WITH AUTOMATIC GAIN CONTROL MODE DISABLED (TLBC.6 = 1) ............................ 165
Table 25-6. TRANSFORMER SPECIFICATIONS................................................................................................... 175
Table 28-1. TRANSMIT ERROR INSERTION SETUP SEQUENCE ...................................................................... 195
Table 28-2. ERROR INSERTION EXAMPLES ....................................................................................................... 197
Table 35-1. INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE............................................................ 220
Table 35-2. ID CODE STRUCTURE ....................................................................................................................... 221
Table 35-3. DEVICE ID CODES.............................................................................................................................. 221
Table 35-4. BOUNDARY SCAN CONTROL BITS .................................................................................................. 223
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