DS21455 Maxim Integrated Products, DS21455 Datasheet - Page 17

• Manufacturer Part Number: DS21455
• Description: Network Controller & Processor ICs Quad E1-T1-J1 Single -Chip Transceiver (S
• Manufacturer: Maxim Integrated Products

Specifications of DS21455

• Product: Framer
• Number Of Transceivers: 4
• Data Rate: 64 Kbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 328 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

4. DS21455/DS21458 DELTA
This section describes the differences between the DS21455 and DS21458.
4.1 Package
DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the
DS21Q55.)
DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA
4.2 Controller Interface
DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver.
DS21458: The CPU interface has 10 address lines with a single chip select. The upper address lines, A8
and A9, act as coded transceiver selects.
4.3 ESIB Function
The ESIB function provides a fast method of determining interrupt and alarm status when multiple ports
(up to 8) are being controlled by a single processor.
DS21455: The three ESIB signals are brought out for each transceiver. The user must externally
configure the ESIB group.
DS21458: The ESIB signals are internally bused and only a single set of signals are brought out to enable
the connection of another DS21458 into an 8-port ESIB.
4.4 Framer/LIU Interim Signals
Access to the clock and bipolar data signals between the framer and LIU function may be used for
specialized applications. An internal MUX connects the framer and LIU if these signals are unused. The
MUX is controlled via the LIUC/TPD pin and LIUC bit in the LBCR register. The unused inputs must be
connected to ground.
DS21455: The user has access to all clock and data signals between the framer and LIU on all
transceivers as shown in
DS21458: The user has limited access to clock and data signals between the framer and LIU on all
transceivers as shown in
Figure
Figure
4-1.
4-2.
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