DS26504LN Maxim Integrated Products, DS26504LN Datasheet - Page 20

• Manufacturer Part Number: DS26504LN
• Description: Network Controller & Processor ICs T1-E1-J1-64kHz Compo 4kHz Composite Clock
• Manufacturer: Maxim Integrated Products

Specifications of DS26504LN

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64

4.5 JTAG
WR (R/W)/
ALE (AS)/
RMODE2
TMODE3
A7/MPS1
RD(DS)/
NAME
NAME
JTCLK
JTRST
JTMS
JTDO
JTDI
RLB
CS/
TYPE
TYPE
O
I
I
I
I
I
I
I
I
Active-Low Read Input-Data Strobe/Receive Mode Select Bit 2
RD
RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side
operating mode.
Active-Low Chip Select/Remote Loopback Enable
CS
signal is used for both the parallel port and the serial port modes.
RLB: In Hardware Mode (BIS[1:0] = 11), when high, remote loopback is
enabled. This function is only valid when the transmit side and receive side are
in the same operating mode.
Address Latch Enable (Address Strobe)/Address Bus Bit 7/MCLK
Prescale Select 1
ALE (AS): In multiplexed bus operation (BIS[1:0] = 00), this pin serves to
demultiplex the bus on a positive-going edge.
A7: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[7].
MPS1: In Hardware Mode (BIS[1:0] = 11), MCLK prescale select is used to set
the prescale value for the PLL.
Active-Low Write Input (Read/Write)/Transmit Mode Select 3
WR
TMODE3: In Hardware Mode, this pin selects the transmit-side operating
mode.
JTAG Clock. This clock input is typically a low frequency (less than 10MHz)
50% duty cycle clock signal.
JTAG Mode Select (with pullup). This input signal is used to control the
JTAG controller state machine and is sampled on the rising edge of JTCLK.
JTAG Data Input (with pullup). This input signal is used to input data into
the register that is enabled by the JTAG controller state machine and is sampled
on the rising edge of JTCLK.
JTAG Data Output. This output signal is the output of an internal scan shift
register enabled by the JTAG controller state machine and is updated on the
falling edge of JTCLK. The pin is in the high-impedance mode when a register
is not selected or when the JTRST signal is high. The pin goes into and exits the
high-impedance mode after the falling edge of JTCLK.
Active-Low JTAG Reset. This input forces the JTAG controller logic into the
reset state and forces the JTDO pin into high impedance when low. This pin
should be low while power is applied and set high after the power is stable.
The pin can be driven high or low for normal operation, but must be high for
JTAG operation.
: This active-low signal must be low to read or write to the device. This
: In Processor Mode, this pin is the active-low write signal.
(
DS
): DS is active high when BIS[1:0] = 01. See the bus timing diagrams.
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FUNCTION
FUNCTION